30 results about "Racetrack memory" patented technology

Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.

The invention discloses a track memory based on magnetic skyrmions, belonging to the technical field of magnetic devices. Including antiferromagnetically coupled double-track magnetic nanoribbons, the magnetic nanoribbons are divided into information writing part, information storage part and information reading part along the track direction, and the binary number 0 or 1. Magnetic skyrmions move from the information writing part to the information reading part along the track direction of the double-track magnetic nanobelt; the magnetic skyrmions periodically move in one of the tracks of the double-track magnetic nanobelt where the information writing part is located Generated, the generated magnetic skyrmions determine whether to change the polarity according to the written data, and then determine whether to move to another track of the double-track magnetic nanoribbon; the information storage part is divided into multiple tracks along the direction of the magnetic nanoribbon A storage unit, each storage unit stores a magnetic skyrmion; the information reading part is used to read the polarity of the magnetic skyrmion passing therethrough.

A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

The invention provides a data programming method, a memory control circuit unit and a memory storage device. The method comprises the steps of setting a first class entity erasing unit as a current writing-in region and recording the current writing-in data size. The method further comprises the step of calculating a data size threshold value according to the first class entity erasing unit. The method further comprises the step of receiving data. The method further comprises the steps of adopting a first programming mode for programming the data to at least one first class entity erasing unit if the current writing-in data size is smaller than the data size threshold value; setting a second class entity erasing unit as a current writing-in region if the current writing-in data size is not smaller than the data size threshold value, and adopting a second programming mode for programming the data into at least one second class entity erasing unit. The problem that a rewritable type racetrack memory module cannot be used due to the fact that the erasing frequency of some entity erasing units is excessively large can be avoided.

The invention discloses a coding method of a racetrack storage position error correcting code and an error correcting method. The coding method of the correcting code comprises the steps of coding positions of one or more read-only access ends of a racetrack memory stripe (RS) relative to the RS as circulating codes, storing the circulating codes into the RS, enabling the position of the RS to correspond to partial circulating codes read from the RS at the moment, obtaining a position code by virtue of the circulating codes, and utilizing the position code as an error correcting code of the racetrack storage position. The circulating code is set as a continuous sequence of a plurality of circulating units, and the bit number of each circulating unit is one or more bits. According to the error correcting method, the error-type position error can be detected and corrected by comparing the position code stored in the access end position of a register and a position code obtained by decoding the circulating codes stored in the racetrack storage stripe, so that the problem of the error of the error-type position can be effectively solved.

The invention discloses a magnetic domain wall writing unit and method based on a multiferroic heterogeneous structure, comprising: a bottom electrode layer connected to a pulse voltage source; a piezoelectric layer made of ferroelectric material and arranged on the bottom electrode layer ; The top electrode layer is arranged on the piezoelectric layer, including a number of top electrodes connected to the pulse voltage source; the magnetic layer is on the same layer as the top electrode, made of ferromagnetic material, and connected to the track memory; wherein the iron of the magnetic layer Magnetic materials have magnetic anisotropy and have magnetostrictive properties. Apply pulse voltage to the top electrode and bottom electrode layer to generate strain in the piezoelectric layer, the strain is transmitted to the magnetic layer and induces magnetic domain walls, and the magnetic domain walls are driven to the track memory; adjust the pulse voltage to change the strain of the piezoelectric layer level, and then write different data. The invention utilizes the inverse piezoelectric effect and the inverse effect of magnetostriction to realize high storage density and low power consumption magnetic domain wall writing.