124results about How to "High speed read" patented technology

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

A solid-state imaging device is provided and includes: a substrate; a plurality of photoelectric conversion elements arranged in a one-dimensional or two-dimensional array above the substrate, the plurality of photoelectric conversion elements being divided into a plurality of photoelectric conversion element groups; a plurality of semiconductor substrates between the substrate and the plurality of photoelectric conversion elements, each of the plurality of semiconductor substrates corresponding to each of the plurality of photoelectric conversion element groups; and a signal output section in the plurality of semiconductor substrates. The signal output section outputs a signal corresponding to an electric charge generated in each photoelectric conversion elements of a photoelectric conversion element group corresponding to a semiconductor substrate.

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as a drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of a reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

A reading circuit for reading information stored in a memory cell includes a current supply circuit for supplying a current to a bit line connected to the memory cell; a comparison circuit for comparing a potential of the bit line supplied with the current by the current supply circuit with a reference potential so as to output the information stored in the memory cell; a disconnection circuit for electrically disconnecting the comparison circuit and the memory cell from each other under a prescribed condition; a charge circuit for charging the bit line, the charge circuit stopping charging of the bit line when the potential of the bit line exceeds a prescribed potential; and a discharge circuit for discharging the bit line when the potential of the bit line exceeds the prescribed potential.

To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells. The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor memory cells are arranged in a matrix, each nonvolatile semiconductor memory cell having an island semiconductor layer in which a drain diffusion layer formed in the upper part of the island semiconductor layer, a source diffusion layer formed in the lower part of the island semiconductor layer, a charge accumulation layer formed on a channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge accumulation layer are formed. Further, bit lines connected to the drain diffusion layer are laid out in a column direction, control gate lines are laid out in a row direction, and source lines connected to the source diffusion layer are laid out in the column direction.

In a wireless communication system including source devices (2, 3) for transmitting video signals by wireless, a sink device (1) for receiving the transmitted video signal and displaying the received video signal on a display device (13), the sink device (1) reads out EDID information from a ROM (11) and transmits wireless-data signal including it by wireless to source devices (2,3). The source devices (2, 3) receive by wireless the wireless-data signal including the EDID information transmitted by wireless and transmit video signals to the sink device (1) by wireless on a basis of the EDID information.

An image forming apparatus has a printing section and a document reading section. The printing section prints on paper while transporting it. The document reading section includes a document transport portion which automatically transports, sheet by sheet, a document placed thereon. The document reading section generates image data by reading the document. The document reading section is operable in an ordinary reading mode in which it reads the document at a previously determined ordinary speed and in a quiet reading mode in which it reads the document at a quiet speed lower than the ordinary speed. The document reading section reads the document in the quiet reading mode when the printing section is not printing and in the ordinary reading mode when the printing section is printing.

A fluorescence correlation spectroscopy analyzer 1 is equipped with an excitation light illuminating optical system 21, a fluorescence imaging optical system 22, a CCD camera 15, and a data analyzer 16. The excitation light illuminating optical system 21 illuminates excitation light onto a predetermined region of a measured sample S. The fluorescence imaging optical system 22 images the fluorescence generated at the measured sample S onto the photodetection surface of the CCD camera 15. The CCD camera 15 performs photoelectric conversion of the fluorescence made incident onto the photodetection surface in accordance with the respective pixels and outputs the charges generated by the photoelectric conversion as detection signals from an output terminal. The data analyzer 16 inputs the detection signals based on the charges generated at the pixels, among the pixels of the CCD camera 15, that belong to an analyzed pixel set and computes autocorrelation functions of the input detection signals according to each pixel. A fluorescence correlation spectroscopy analyzer, which is enabled to perform fluorescence correlation spectroscopy analysis on multiple points of a measured sample simultaneously and at high speed, is thus provided.

A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

The invention relates to a device and a method for comprehensively controlling and protecting a pump set of a diesel engine, which are applied to the comprehensive control and protection of the pump set of the emergency / fire-fighting diesel engine. The device comprises a core operation unit, a signal output unit, a signal input and processing unit and a communication protocol conversion unit; a first single chip machine is connected with the diesel engine, a host computer and an LCD screen; and the first singlechip is also connected with a second singlechip. The method orderly comprises the following steps of self-test, start, process control of the operation of the machine set, state check in the operation of the machine set, control of shutdown of the machine set and completion. The control system has the advantages of high accuracy, strong emergency treatment capability for timely alarm control, low cost, high cost-performance ratio, small volume, simple structure, convenient use and high degree of automation; and the control and protection method can timely and accurately judge various faults occurring during the operation of the machine set and alarm, and make the automatic and accurate control, and the control program is reasonable, simple and reliable.