1845results about How to "Avoid elevation" patented technology

It was an objective of the present invention to provide a susceptor which can prevent a increasing phenomenon of the dopant concentration of the epitaxial layer at the peripheral portion of the wafer. By providing a through-hole 7 passing through to a rear side at the outer peripheral side of the wafer inside the wafer pocket 6, a down flow of a reacting source gas from the upper surface of the susceptor 5 is formed, so that the unwanted flow of the dopant species being exhausted at the rear surface onto the wafer surface can be avoided. As a result, a raise in the dopant concentration at the outer peripheral portion of the epitaxial layer 9 can be controlled.

A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour.

Embodiments of the invention may be directed to apparatuses for securing and sealing tissue and related methods of use.