70 results about "Pipeline (software)" patented technology

Systems, apparatuses, methods, and software for processing data in pipeline architectures are provided herein. In one example, a pipeline architecture is presented. The pipeline architecture includes a plurality of processing stages, linked in series, that iteratively process data as the data propagates through the plurality of processing stages. The pipeline architecture includes at least one other processing stage linked in series with and preceded by the plurality of processing stages and configured to iteratively process the data a number of times based at least on an iteration count comprising how many times the data was iteratively processed as the data propagated through the plurality of processing stages.

Certain aspects of the present disclosure provide techniques for managing the deployment of software applications based on application performance data. Embodiments include transmitting, to a performance testing system, information identifying a test build of a software application component in a first deployment environment in a software development pipeline to test. Performance information for the test build of the software application component is received from the performance testing system. The received performance information for the test build of the software application component is compared to one or more of predetermined performance parameters or historical performance data for the software application component. Based on the comparing, the system takes one or more actions to manage deployment of the test build of the software application component to a second deployment environment in the software development pipeline.

The invention discloses an FPGA-based acceleration platform and a design method for a gene sequencing string matching algorithm. The acceleration platform includes a PS (Program System) end and a PL (Program Logic) end, and the PS end includes a general-purpose processor and a DRAM to complete the software-side code operation and control of a hardware part, the PL end contains a plurality of IP cores that can be solidified according to requirements to achieve corresponding tasks. First, the general-purpose processor writes string data into the DRAM, and then the FPGA reads the string data fromthe DRAM and starts calculation, and the calculation result is written into the DRAM, and finally the general-purpose processor reads the matching result from the DRAM. The accelerator of the invention deploys multiple independent IP cores for calculation on the FPGA and the IP cores run in a pipeline mode, so that programmers without hardware knowledge can easily obtain good performance by usingexisting FPGA resources.

As provided, a method of integration of hardware, software and vendor labor in software development pipeline management that comprises providing, for each of multiple projects in a software project pipeline, a set of inputs that includes 1) timing, 2) demand inputs, 3) supply inputs. The method further comprises aggregating the inputs. The method further comprises identifying one or more constraints in the software development pipeline when the demand inputs and the supply inputs are not in balance with the input timing.

A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

The invention discloses a firewall system of a user mode pipeline architecture. A control plane is responsible for management and control functions of the system and redirects a message sent from a management port to a kernel protocol stack; a data plane is responsible for main service functions, works in a user mode and can bypass a complex Linux kernel protocol stack to directly obtain messagesfrom a network card. The data plane decomposes firewall function software into a plurality of function modules, each function module is bound to an independent CPU core, one CPU core serves as a maincore and is responsible for receiving messages, data packet receiving and sending are achieved in a polling mode, and an assembly line framework is formed. The firewall system belongs to a software architecture which bypasses a system kernel and is suitable for a firewall function, a network card driver is usually realized in the kernel, the firewall system is realized again in a user mode, the system directly acquires a message from the network card, and the problem of low processing efficiency caused by a traditional firewall Linux kernel is effectively solved.

Computing systems, for example, multi-tenant systems deploy software artifacts in data centers created in a cloud platform using a cloud platform infrastructure language that is cloud platform independent. The system receives pipeline templates including templating expressions that can be substituted with values for generating pipelines. A pipeline can be executed to perform a set of actions associated with continuous delivery of a software artifact. The system stores sets of partially hydrated pipeline templates. The partially hydrated pipeline templates can be compiled into executable pipelines associated with services configured on a datacenter of a cloud platform. The system stores different versions of pipeline templates as deployment packages. The system stores version pointers that identify specific deployment packages that are selected when a software release is deployed. The version pointers allow the deployment package to be updated in case of roll back or for deploying more recent changes.

The invention discloses a data conversion method based on a pipeline three-dimensional model, the combination of SPOOLGEN and multiple software becomes a mainstream working mode at present, but the combination of SPOOLGEN and E3D has the defects that ISO drawings output by SPOOLGEN are inconsistent, the workload is increased for designers to check drawers, the design and construction efficiency isreduced, and the design cost is increased. According to the method, two-dimensional projection is carried out on a pipeline three-dimensional model in E3D software, Excel tables are used for countinginformation of all elements in two-dimensional projection, three-dimensional models of all the elements are established through SolidWorks according to table data, the three-dimensional models of allthe elements are modified, the pipeline three-dimensional model and the elbow three-dimensional model established by SolidWorks are enabled to be consistent with the corresponding pipeline three-dimensional model and elbow three-dimensional model in the SPOOLGEN, the splicing of each three-dimensional model element is completed at the SPOOLGEN, the corresponding valve model is replaced at a specified position, finally a standard ISO graph is output in the SPOOLGEN, and therefore the three-dimensional model in the E3D software obtains a SPOOLGEN standard ISO graph format.

Computing systems, for example, multi-tenant systems deploy software artifacts in data centers created in a cloud platform using a cloud platform infrastructure language that is cloud platform independent. The system generates pipelines for deploying software artifacts in data center entities configured in a cloud platform. The system allows partial execution of pipelines such that the pipeline can be executed again to complete execution of the remaining stages. The system maintains state of the pipeline execution and checks the state to determine whether a stage should be executed during subsequent executions. The system allows a failed stage to be retried multiple times based on a retry strategy. A retry strategy may depend on the data center entity in a hierarchy of data venter entities of a data center.

In order to avoid hardware pipeline breaks and also to enhance performance when emulating a target system in a host system employing a central processing unit including a plurality of execution units, three major pieces of processing that are required for handling every emulated instruction are overlapped. This overlap includes: 1) the instruction fetch of the emulated instruction by the emulation software, 2) the branching of the emulation code based upon the opcode of the emulated instruction to be executed and 3) the actual execution processing for each emulated instruction. The branching of the emulation code, depending upon the opcode of each instruction, utilizes special instructions configured to minimize pipeline breaks on the host system hardware and thus to minimize the effective minimum host system processing time for the simplest emulated instructions.

Computing systems, for example, multi-tenant systems deploy software artifacts in datacenters created in a cloud platform using a cloud platform infrastructure language that is cloud platform independent. A system receives pipeline templates including templating expressions that are substituted with values for generating pipelines. A pipeline is executed to perform a set of actions associated with continuous delivery of a software artifact. The system stores sets of partially hydrated pipeline templates. The partially hydrated pipeline templates are compiled into executable pipelines associated with services configured on a datacenter of the cloud platform. The system stores different versions of pipeline templates as deployment packages. The system stores version pointers that identify specific deployment packages that are selected when a software release is deployed. The version pointers allow the specific deployment packages to be updated in case of roll back or for deploying more recent changes.

Provided is a thermal compensation design method for a high-temperature air pipeline. The thermal compensation design method includes the steps of using UG NX commercial software under a mechanical pipeline layout module to build a pipeline geometric model containing seven types of mathematical variables, carrying out pre-processing through finite element analysis software ANSYS, material parameters are given according to GH536, wherein an elasticity modulus E is equal to 187 GPa, and poisson ratio mu is equal to 0.3, utilizing boundary conditions and imposed displacement boundary conditions and temperature field load, calculating and obtaining the stress conditions of the pipeline, adjusting pipeline layout paths, carrying out calculation again according to the second content to the fourth content, and obtaining a new calculation result, that is, the maximum stress value is smaller than yield limit of materials, and yield strength reserve factor is larger than 1.5, and therefore the design requirements are met. The thermal compensation design method has the advantages of improving design reasonability and ensuring that the high-temperature air pipeline meets the requirements of engines for long service life and high reliability.

The invention provides a pipeline engineering display method, device and equipment and a storage medium, and belongs to the technical field of software platforms. The method comprises the steps: obtaining to-be-displayed two-dimensional pipeline data and three-dimensional pipeline data of a preset position; according to the position information of the three-dimensional pipeline data, associating the three-dimensional pipeline data to a position corresponding to the position information in the two-dimensional pipeline data, and obtaining a to-be-displayed image; displaying an image to be displayed. According to the invention, various data information of the pipeline can be displayed more comprehensively and visually.

The invention discloses a low-power-consumption register allocation compiling optimization method. The method comprises the following steps: S1, analyzing a hotspot function and a cycle segment of a program; s2, counting the execution frequency of the dependency statement in the hotspot code segment; s3, registering a life cycle of a temporary variable in the statement with the dependency relationship; s4, closing instruction scheduling optimization related to the performance of the dependency statement to prevent instruction scheduling performed due to consideration of pipeline performance; s5, performing life cycle analysis in the basic block on the temporary variable of each dependency relationship; s6, carrying out cross-basic-block life cycle analysis on the temporary variable of eachdependency relationship; s7, traversing all the basic blocks, and tracking definition and use points (defineuse) of the temporary variables marked as low-power-consumption optimization; and S8, performing Wset instruction loop extraction optimization. According to the invention, the system operation power consumption is optimized to a certain extent, the software and hardware development cost islow, the method for reducing the power consumption is simple and direct, and the low-power-consumption potential of the register is mined to the maximum extent on the premise of considering the performance.