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32 results about "Code size" patented technology

Size codes have fields for Primary and Secondary sizes. • For apparel, the Primary Size refers to body size; the Secondary Size describes a Proportion, such as a waist or neck size, trouser rise, a cup size, or a general body proportion such as Petite.

LDPC (low density parity check) code size adjustment by shortening and puncturing

LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Variable register and immediate field encoding in an instruction set architecture

A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.
Owner:ARM FINANCE OVERSEAS LTD

System and method for bar code rendering and recognition

A method and system for rendering accurate bar code images in a distributed network wherein a plurality of different types of rendering devices, such as printers, having different resolution characteristics are connected for rendering such images. The resolution of a connected rendering device is detected and the bar code image to be rendered by such device is scaled to effect proper alignment of the resolution units of the bar code and the rendering device whereby the need for interpolation is effectively obviated. The bar code is scaled by a whole integer multiplier of the minimum bar code size based upon at least one dimension of the print area of the bar code display and the resolution characteristic of the rendering device. The bar code image is aligned or mapped and is centered in the display area with equal units of the excess print area on either side of the image. By avoiding the need to interpolate print data by the rendering device, the bar code rendering system defeats inaccuracies in detection and decoding and provides a more reliable data recovery system.
Owner:CATALINA MARKETING CORP

Method and an apparatus for system encoding bitstreams for seamless connection

An encoding method for producing specific encoded data by calculating the data occupancy of a decoding buffer memory of a particular size that is used when decoding the encoded data during reproduction, defining the allocated code size of a particular period based on the calculation result, and compression coding the signal of a particular period to the allocated code size. The data occupancy is calculated on the assumption that virtual encoded data is transferred to the decoding buffer memory following the transfer of the first-encoded data to the decoding buffer memory. The data occupancy when the last data in the first encoded data is decoded is calculated as the final buffer occupancy Be. The data occupancy when the encoding process producing the second encoded data is begun is an initial buffer occupancy Bi where the initial buffer occupancy Bi is less than the final buffer occupancy Be, and thus allocated code size is defined based on the change in the data occupancy.
Owner:PANASONIC CORP

Computer program code size partitioning system and method for multiple memory multi-processing systems

The present invention provides for a method for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic.
Owner:IBM CORP

Image code estimation

Estimation of the code size of variable length encoding of quantized DCT coefficients by summation over histogram bins of products of number of bin members and a code size of an average run of zero coefficients coupled with a representative level from the bin. The estimation provides low-complexity feedback for quantization level adjustment to obtain variable length code size target without actual performance of a quantization level plus variable length encoding.
Owner:MAGFUSION +1

Image encoding apparatus and decoding apparatus, and control method thereof

This invention maintains pixels as a source of a high frequency component such as a character and generates the encoded data having a fixed length for one block. A block generator reads out image data of one block from image data. An extractor extracts a color of a pixel having high frequency component, and generates information identifying pixels of the extracted color and those of non-extracted color. A first encoder lossless-encodes the identification information. A detector detects the data size of the generated encoded data. A substitution unit calculates the average value of colors of the pixels having the non-extracted color, substitutes the color of the pixels having the extracted color by the average value. A second encoder encodes the pixels after the substitution. An adjustment unit adjusts the data size of the encoded data from the second encoder in accordance with the code size detected by the detector.
Owner:CANON KK

Equipment and method for parallel mode matching

The invention provides equipment and a method for parallel mode matching. The equipment comprises a conversion device and a matching device, wherein the conversion device is used for combining a plurality of modes into a mode group and connecting the ith character of each mode in the mode group to form the ith character vector, wherein i is equal to 1, 2, 3 to N, and N is the character number contained in the mode having most characters in the mode group; and the matching device is used for respectively comparing each character in the ith character vector with the ith character in the data stream from the first character vector to carry out parallel mode matching. The invention has the advantages that the utilization ratio of a processor is greatly increased by using SIMD commands, the cost for memory access is lower, the size of codes is reduced by using fewer commands, and the branch delay is minimized.
Owner:IBM CORP

Packing envelope printing method for automatic medicine packing machine

InactiveUS20080099562A1Prevents limited representationPreventing error and defect in printing positionPharmaceutical containersMedical packagingBarcodeComputer science
A packing envelope printing method for an automatic medicine packing machine includes steps of calculating data amount, deciding excess data, in which whether the calculated data amount exceeds a reference data amount that is preset is decided; selecting bar code printing method according to the decision, in which one dimension bar code or two dimension bar code is selected and data printing, in which a bar code and predetermined print data are printed on the front surface of the packing envelope with the selected bar code printing method. The method also includes steps of deciding bar code size and position, designating additional print data, previewing, correcting printing error, and printing a header packet and a footer packet.
Owner:JVM CO LTD

Method and system for quantitatively estimating code size of new requirements based on weight adjustment

The invention discloses a method and a system for quantitatively estimating the code size of new requirements based on weight adjustment. The method comprises the following steps of: performing characteristic extraction according the conventional N requirements of a software project; selecting the characteristic extraction data of m requirements, setting the characteristic extraction data of each requirement to be RSi, setting an adjustment parameter gamma of the software project to be 1 and calculating an estimated value ESi of the code size of the requirement RSi; calculating the ratios gammai of each estimated value to a real value, and taking the value of the adjustment parameter gamma as an average value of all the ratios gammai; performing the characteristic extraction on the new requirements of the software project; calculating distances Dij between each new requirement Rnewi and the conventional requirements; calculating the weight Wij of influence among the requirements; and calculating the estimated value Ei of the code size of the new requirements Rnewi according to a formula. In the method of the invention, similarity between the new requirements and the conventional requirements of the software project is calculated, and the characteristic data of all the conventional requirements is used, so the to-be-generated code size of the new requirements can be accurately quantized.
Owner:INST OF SOFTWARE - CHINESE ACAD OF SCI

Assembler capable of reducing size of object code, and processor for executing the object code

InactiveUS20050108698A1Size of object is limitedSmall sizeSoftware engineeringProgram controlObject codeInstruction code
An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.
Owner:RENESAS TECH CORP

LDPC (low density parity check) code size adjustment by shortening and puncturing

LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Method for reducing code size of program in code memory

A method of reducing a code size of a program by controlling a control flow of the program using software in a computer system is disclosed. The method includes the steps of storing a first program count of a first instruction in a first buffer when an error occurs while the first instruction having an Operand including Offset and Length is being executed among a plurality of instructions loaded in the code memory, changing a current program count of the code memory to a second program count which is obtained by adding the Offset to the first program count, storing a second instruction, which is located at a position shifted from the second program count by a value of the Length, in a second buffer, replacing the second instruction with a third instruction, which is not recognized by a microprocessor, replacing the third instruction with the second instruction stored in the second buffer when an error occurs while the third instruction is being executed, and changing the current program count of the code memory to a predetermined program count next to the first program count stored in the first buffer.
Owner:SAMSUNG ELECTRONICS CO LTD

Image compression apparatus, image decompression apparatus, image compression method, image decompression method, program, and recording medium

An image compression apparatus includes a code size setting unit setting one or more code sizes, a compressing unit compressing an image that is divided into plural image quality levels in accordance with the code sizes, and a code generating unit generating code being dividable into each code size.
Owner:RICOH KK

Veterbi decoding method for convolutionally encoded signal

InactiveUS20080152044A1Reduce complexitySuitable for hardware implementationError preventionOther decoding techniquesComputer architectureSoftware
An improved Viterbi decoding method for convolutionally encoded signals is disclosed. By using the method of the present invention, a trellis of Viterbi Algorithm (VA) for convolutionally encoded SBAS signal, for example, are arranged into butterflies. The butterflies are classified into groups according to branch metrics. Therefore, the butterflies can be effectively processed since the same butterfly processing kernel can be used repeatedly. Therefore, the code size and processing time can be reduced, so that Viterbi Algorithm can be more easily implemented by software.
Owner:MEDIATEK INC

Method for searching name card by entering initials of the first three characters of the name

InactiveCN1972330AQuick to enterBoth lookup accuracySubstation equipmentAlgorithmTheoretical computer science
This invention provides one Chinese intelligent telephone machine to realize three degree first part technique and means and human to machine operation for formative definition and rules for final explanation, wherein, it combines first name pinyin character in alphabet order and character GB or UNICODE code size.
Owner:何宇新

Method and apparatus for code size reduction

A method for code size reduction, which comprises determining basic blocks in an IR module; grouping the basic blocks having duplicate code into groups; providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes; determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; removing duplicates in one group to obtain a module having one processed group; determining a weighted size of the module having one processed group; and comparing the weighted size of the module to the weighted size of the module having one processed group.
Owner:NATIONAL TSING HUA UNIVERSITY

Apparatus and method using hybrid length instruction word

A parallel processing computer architecture utilizes hybrid length instruction words that mix vectors and Very Long Instruction Word (VLIW) or other parallel processing instructions to enable data-parallel and task-parallel instructions to be run simultaneously with reduced redundancy and code size inefficiency.
Owner:RESILIENT SCI

Commodity arc-shaped QR code conversion method

The invention discloses a commodity arc-shaped QR code conversion method, comprising the following steps: solving a commodity shape curve equation by adopting a function equation through a mathematical method according to a known special shape size of a commodity surface; obtaining a known commodity plane QR code size, a known installation position and a known commodity structure size, projectingthe commodity plane QR code to a corresponding position of a commodity special-shaped surface, and calculating the size of a commodity arc-shaped QR code; solving to obtain the size of the QR code pattern projected to the special shape of the commodity by using a commodity shape curve equation; calculating a frame size value of each region in the arc-shaped QR code pattern; and calculating arc sizes of all information areas in the commodity QR code pattern, and finally generating commodity arc QR code data. For the method for converting a planar QR code into an arc-shaped QR code provided by the invention, a planar QR code can be correspondingly formed during reading when the planar QR code is adhered to the special-shaped surface of a commodity, so that the reading accuracy of the QR codeinformation is ensured.
Owner:广东省广袤科技有限公司
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