514 results about "Memory mapping" patented technology

A memory mapping unit requests allocation of a remote memory to memory mapping units of other processor nodes via a second communication unit, and requests creation of a mapping connection to a memory-mapping managing unit of a first processor node via the second communication unit. The memory-mapping managing unit creates the mapping connection between a processor node and other processor nodes according to a connection creation request from the memory mapping unit, and then transmits a memory mapping instruction for instructing execution of a memory mapping to the memory mapping unit via a first communication unit of the first processor node.

The present invention is directed to a new visualization platform for the interactive exploration of large datasets. The present invention integrates a collection of relevant visualization techniques to provide a new visual metaphor for viewing large datasets. It is capable of providing comprehensive support for data exploration, integrating large-scale data visualization with querying, browsing, and statistical evaluation. A variety of techniques are utilized to minimize processing delays and the use of system resources, including processing pipelines, direct IO, memory mapping, and dynamic linking of “on-the-fly” generated code.

A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

The invention provides a virtual machine system based on the management technology of equipment access storage and an equipment access control method thereof. The virtual machine system comprises a virtual machine monitor, an underlying hardware supporting the management technology of storage for equipment input and output, an equipment control module and a plurality of virtual machines; wherein the virtual machine monitor comprises a scheduling module which can schedule different virtual machines to run on a processor, a memory virtualization module used for completing memory management of the virtual system, an interrupt virtualization module, an instruction analyzer, a privilege calling interface used for providing services for privilege entity and a control module of a storage management unit of equipment input and output. In the virtual machine system, one equipment control module corresponds to physical equipment and is responsible for initiating privilege calling to the virtual machine monitor, receiving and executing an equipment port access instruction transmitted by the virtual machine monitor, detecting equipment state and hiding the virtualization equipment resources and the like. In the equipment access method provided by the invention, a client operating system in the virtual machine can access equipment data by a memory mapping mode; and the equipment utilizes the equipment access storage management technology to carry out direct storage access to virtual machine data. The virtual machine system and the equipment access control method lead the equipment performance to be improved greatly, relieve the system performance bottle-neck, and improve safety of equipment access control. The equipment access control method does not need to modify the client operating system, is easy to be realized and has wide application range.

The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution. The technique is based upon identifying at least one conflicting data-block having a memory mapping indication to a designated memory cache-line and preventing the conflicting data-block from being cached. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user.

The invention provides a base station user plane data processing and optimizing method based on a Linux system. The method comprises the steps as follows: package classification is completed by using a package processing acceleration module; the interrupt of package reception is reduced in an intelligent switching manner for interrupt polls; memory copying is avoided by using a core space-user space memory mapping technology; and context switching between a core state and a user state is reduced by using a lock-free queue technology, so that the performance for processing base station user plane data is remarkably improved.

An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.