51 results about "Local logic" patented technology

A local logic solver operates with a local smart valve controller to control and test a local field-mounted emergency isolation valve device, outputting a local indication of trouble on the device, which is mounted in the field away from the facility's central control panel for the process. Accordingly, the operation of the overall system is simplified by eliminating the need for an external computer to diagnose any problems. A local control panel includes an indicator light substantially adjacent to or in close proximity to the device being monitored to alert personnel of detected faults. Detected faults are time-stamped locally to generate documentation and to track the elapsed time, starting when the degraded state of the device was detected and first signaled as a problem.

A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial design by a staisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.

A local logic solver that operates with a local smart valve controller to control, test and monitor performance characteristics of a local field-mounted emergency isolation valve device, outputting a local indication of trouble on the device, which is mounted in the field away from the facility's central control panel for the process. The local logic solver includes a recording function and memory for retrieval of detected faults that are time-stamped and recorded locally to generate documentation and to track the elapsed time, starting when the degraded state of the device was detected and first signaled as a problem; other performance data is also recorded. Accordingly, the operation of the overall system is simplified by eliminating the need for an external computer to diagnose any problems. A local control panel preferably includes pushbuttons and lights used during routine operations of the valve and a fault indicator light substantially adjacent to or in close proximity to the device being monitored to alert personnel of detected faults.

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read / Write commands are issued once per burst access eliminating the need to toggle the Read / Write control line at the device cycle frequency. A transition of the Read / Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input / output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I / O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read / Write commands are issued once per burst access eliminating the need to toggle the Read / Write control line at the device cycle frequency. A transition of the Read / Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input / output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I / O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

The invention discloses a distributed transaction management method and system based on a distributed logic timestamp. The method comprises the steps of setting transaction starting time of a transaction; if the difference value between the local logic time of the data node and the local logic time of the coordination node exceeds a preset threshold value, timing the local logic time of the data node, enabling the coordination node to roll back the transaction, and retrying the transaction after the time of the coordination node is timed; if the difference between the transaction pre-submission time and the transaction start time is greater than the transaction tolerance error of the transaction, sending the transaction pre-submission time and the pre-submission message of the transactionto all data nodes participating in the transaction; and selecting one data node as an arbitration node to arbitrate the timestamps of the two different transactions according to the difference value condition of the timestamps of the two different transactions. According to the invention, the overhead of the network can be reduced while the requirements of distributed storage and processing are met, so that the overall performance of the system is effectively improved.