51results about How to "Save current" patented technology

A method and system for reducing self-refresh current requirements in a includes a DRAM chip that is sectioned into a number of segments. The entire DRAM chip is tested upon manufacture to determine the relative decay rates for each cell in the DRAM. For each segment, the refresh rate for that segment is selected based on the fastest decay rate for a DRAM cell in the segment. The DRAM is configured for refreshing memory cells during a self-refresh at different refresh rates for different segments. The refresh period is controlled for individual segments using techniques, such as programmable logic or fuses, to skip certain self-refresh cycles for those segments capable of operating at lower refresh rates. The refresh period in memory segments with strong memory cells can be reduced, thereby conserving current required to be drawn.

A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles. Once the DCC is locked during its initialization, the reduced-frequency operation of DCC further saves current consumption. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

A system and method for communicating between a controller and a device is provided: The controller communicates with the device over a communication link. The controller shutting off a power supply that is connected to the communication link, for example, due to inactivity parameters. The device generating a wake up signal and transmitting the wake up signal from the device to the controller while the power supply is shut off.

In a method for ascertaining the phase currents of an electric machine having a power converter and a stator with a phase number of four or more, the phase currents of a measuring number of measuring phases is measured, which is at least two and is lower by at least two than the phase number, and the phase currents of the remaining phases are arithmetically determined from the measured phase currents, at least the measured phase currents, a spatial angle of the measuring phases and a spatial angle of the remaining phases being used for the arithmetical determination.

A cutting tool is provided having a marking feature to facilitate the cutting of materials at desired lengths. The tool includes a laser that provides a beam for marking the material at a determined length based on the angle that the beam forms with the cutting axis of the tool. The tool may be configured so that the beam can be emitted on either side of the tool. The tool may be reconfigured so that the angle of the beam relative to the cutting axis of the tool is selectively adjustable.

A voltage detector (200) for monitoring an input signal and outputting a detection signal at an output when a voltage of the input signal meets a first threshold having: an input configured for receiving the input signal; a voltage reference circuit for receiving an input voltage and producing a reference voltage having a maximum value independent of the input voltage; and a trigger configured to compare the input signal and the reference voltage and to output a detection signal to the output when the voltage of the input signal reaches the first threshold. The voltage reference circuit comprises a reset input connected to either the input or the output and is configured to reduce the reference voltage when a predetermined reset signal is received. The voltage reference circuit may include: an input for receiving the input voltage; a first current controlling element (210), such as a diode, which allows current to flow as an increasing, non-linear function of voltage at least within a first range of voltages; a second current controlling element (240), such as a transistor, which allows current to flow as an increasing, non-linear function of voltage at least with a second range of voltages; and an output at which the output reference voltage is produced. The first current controlling element and the second current controlling element are connected in series between the input and a common reference, with the second current controlling element between the first current controlling element and a common reference, the output comprises a node between the two current controlling elements, the first and second range of voltages overlap and the second current controlling element is configured to vary the function by which it allows current to flow in dependence on the input voltage.

The present invention provides a system and method for optimizing power consumption in mobile devices. The system comprises a speech codec encoder module and a speech codec decoder module. The number of CPU / DSP / VLIW processor cycles taken to encode and decode the speech signals are significantly reduced to draw lower current by the mobile device. The significant reduction of processor cycles in the speech codec modules enables reduction of power consumption in the talk time. Thus, the invention provides a simple method of optimizing power consumption by reducing number of processor cycles to compress / decompress speech signal of the speech codec modules in mobile devices.

A memory circuit comprises a memory cell array with dynamic memory cells arranged on word lines and bit lines, a selection unit providing selection information and a refresh circuit selecting the memory cells in each case in dependence on the selection information and refreshing the selected memory cells so that any information stored therein is retained in each case.