41results about How to "Reduce read errors" patented technology

The invention discloses a method and a device for reading data. The method comprises the following steps: when a read instruction for reading a target address is received, judging whether data pointed by reading of the target address are cached in a preset cache region; if the data pointed to reading of the target address are cached in the preset cache region, searching a cache address corresponding to the reading of the target address according to a first mapping relation, and reading the data pointed by the cache address from the preset cache region, wherein the first mapping relation is used for recording a corresponding relation between the target address and the cache address; if no data pointed by reading of the target address are cached in a preset cache region, reading the data pointed by reading of the target address from a nonvolatile storage space. By the mode, read data errors caused by write interference can be reduced.

A flash memory device includes a normal memory cell array for storing data, a normal page buffer for inputting data to the normal memory cell array or reading data stored in the normal memory cell array, one or more reference memory cell blocks for storing reference data, one or more reference page buffers for inputting reference data to the reference memory cell blocks or reading reference data from the reference memory cell blocks, and outputting a reference control signal, and one or more latch signal generators for generating first and second latch control signals supplied to the normal page buffer and the reference page buffers in response to the reference control signal. A reference bit line signal is formed using the reference memory cell block, the reference page buffer, and the latch signal generator.

The present application discloses a method and device for reading data, wherein, the method includes: when receiving a read command including a read target address, judging whether the read target address points to a cache in the preset buffer area If there is, find the cache address corresponding to the read target address according to the first mapping relationship, and read the data pointed to by the cache address in the preset cache area, wherein the first The mapping relationship is used to record the corresponding relationship between the target address and the cache address; if not, read the data pointed to by the read target address from the non-volatile storage space. Through the above manner, errors in reading data caused by write interference can be reduced.

The invention provides a flash memory device and a programming method thereof. The flash memory device comprises a substrate, wherein the substrate is of a cylindrical structure; a source end and a drain end are respectively arranged at the end parts of the substrate; a grid is coats the middle of the substrate; a first insulating layer is arranged between the grid and the substrate; the grid comprises a control grid and a floating grid parallel to each other; and contact lines are respectively led out of the two ends and are used for applying voltage to the substrate. According to the programming method of the flash memory device, by utilizing a back grid bias assisted hot electron generating mechanism, low voltage can be applied to the drain end, the key size of a split floating grid flash memory is effectively shortened, and the cell density of a flash memory array is increased, namely the memory capacity and density of the flash memory are increased. The movement of hot electrons is assisted by applying bias voltage, enough energy crossing an oxide layer is provided so as to finish compiling, the compiling efficiency of the flash memory is improved, and the compiling current power consumption is reduced.

The invention provides a SONOS flash memory device and a compiling method. The SONOS flash memory device includes a substrate in a cylindrical structure and a gate covering the middle part of the substrate; the ends on both sides of the substrate are respectively a source end and a drain end. , the gate includes a parallel first silicon gate and a second silicon gate, and a first oxide layer is provided between the first silicon gate and the second silicon gate; wherein, the second silicon gate and the substrate include in turn: A second oxide layer disposed on the substrate, a silicon nitride layer disposed on the second oxide layer for storing charges, and a third oxide layer disposed on the silicon nitride layer. The structure can suppress the short-channel effect, resist threshold voltage drift, and effectively shorten the critical size of the flash memory device. The programming method of the flash memory device in the present invention assists the movement of hot electrons by adjusting the voltage of the gate and the drain, provides enough energy to cross the oxide layer to complete the compilation, improves the compilation efficiency of the flash memory, and reduces the compilation current power consumption.

The invention is suitable for the technical field of storage and provides a selection method and a selection system for physical blocks of a 3D flash memory. The selection method comprises the following steps of confirming whether data can be written in a physical page of a latest physical block corresponding to a logic address of a writing operation instruction or not when the writing operation instruction is received; if the data cannot be written in the physical page, determining a blank physical block with the best performance from a blank physical block group of the 3D flash memory; and writing the data in the blank physical block with the best performance. According to the selection method, the performance of each blank physical block is considered in a data writing process, so that the generation of writing errors and read errors can be reduced, the data correctness can be ensured to the maximum extent, and the workload of ECC (Error Correcting Code) error correction is reduced.

The invention is suitable for the technical field of memories and provides a data storage method and a data storage system. The storage method comprises the following steps of directly writing data in a physical page of a latest physical block if the data can be written in the physical page when a writing operation is detected; if the data cannot be written in the physical page, judging the updating frequency of a logic block according to the updating frequency of a physical block chain corresponding to the logic block; and selecting a corresponding blank physical block according to the updating frequency of the logic block, and performing data writing. According to the storage method, the generation of writing errors and read errors can be reduced, the data correctness can be ensured to the maximum extent, and the workload of ECC (Error Correcting Code) error correction is reduced.