Flash memorizer

Abstract

The invention discloses a flash memorizer. The flash memorizer comprises a cylindrical body structure serving as a substrate, wherein the body structure is of an N type silicon structure and comprises a middle portion and two end portions on the two sides of the middle portion, a grid electrode is wrapped on the middle portion in a surrounding mode to form a surrounding grid. The two end portions serve as a source electrode and a drain electrode and respectively comprise a layer of P type doped area. The portion, surrounded by the corresponding P type doped area, of each end portion is led out through a contact line and used for exerting a substrate voltage. A smaller grid length can be obtained, the voltages used for controlling the grid and a floating grid can well control a groove, the percentage of the portion, occupied by a source and drain depletion region through extension, of the total size of the depletion region can be lowered, the short-channel effect can be restrained, threshold voltage drift can be resisted, and reading mistakes of the flash can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a flash memory. Background technique [0002] For NOR flash memory cells, the most important limit to the continued reduction in size is the shortening of the gate length. This is mainly because the channel thermal electron (CHE) injection compilation method requires a certain voltage at the drain terminal, and this voltage has a great influence on the penetration of the source and drain terminals. For short channel devices, the channel thermal electron (CHE) method Not applicable. Another problem is that this limits the programming rate of NOR flash compared to NAND and AND data storage devices. According to the prediction of the document "G. Servalli, et al., IEDM Tech. Dig., 35_1, 2005", the physical limit of the gate length reduction of the traditional flash memory structure is 130nm. [0003] Existing flash memory storage units generally use polysilicon as a floati...

AI Technical Summary

Problems solved by technology

There are inherent defects in the flash memory technology of floating gate transistors. The thin dielectric layer below 100 nanometers will cause leakage, which will lead to data interference and chip failure results.

In addition, devices below the sub-100nm technology node will have a more serious short channel effect (Short Channel Effect), which affects the electrical characteristics of the storage device, making its threshold voltage drift compared with the long channel, resulting in possible readout errors

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