765 results about "Wafer dicing" patented technology

Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the SOI substrate and the assembly substrate, joining the SOI substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

A new method to form a VLSI-photonic heterogeneous system device is achieved. The method comprises providing an optical substrate comprising at least one passive optical component formed therein. An electronic substrate is provided comprising at least one active electronic component formed therein. A plurality of metal pillars are formed through the optical substrate and protruding out a first surface of the optical substrate. A plurality of metal pads are formed on a first surface of the electronic substrate. The optical substrate and the electronic substrate are bonding together by a method further comprising aligning the first surfaces of the optical and electronic substrates such that the protruding metal pillars contact the metal pads. The optical and electronic substrates are then thermally treated such that the metal pillars bond to the metal pads.

A method for fabricating a sensor for chemical and / or biological materials, comprising steps of providing a wafer comprising a plurality of cantilever assemblies, each of the assemblies comprising a cantilever member and a micro-channel plate bonded to the cantilever member, the micro-channel plate further comprising a micro-channel, functionalizing each of the cantilevers by directing a flow of a plurality of functionalizing materials through the micro-channels, and dicing the wafer into a plurality of the sensors. Each of the cantilever assemblies comprises substrate comprising control and sense electrodes deposited on its top side and scribe marks etched on its back side; a cantilever member comprising a cantilever, a seed layer and a contact pad formed on top side of the cantilever member; and the micro-channel plate comprises a micro-channel housing defining the micro-channel etched through the housing, wherein the back side of the cantilever member is bonded to the substrate and the micro-channel plate is bonded to said top side of the cantilever member. Control electronics are incorporated into the substrate for a completely integrated design.