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Reading method of 3D NAND flash memory

A technology of flash memory and storage string, which is applied in the reading field of 3D NAND flash memory, and can solve problems such as read interference and data drift

Active Publication Date: 2018-12-21
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND flash memory structure, three-dimensional arrangements are made according to series and rows. In the prior art, when a certain storage unit is read, it often causes read interference to other storage units adjacent to the storage unit, resulting in data drift

Method used

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  • Reading method of 3D NAND flash memory
  • Reading method of 3D NAND flash memory
  • Reading method of 3D NAND flash memory

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Embodiment Construction

[0016] The specific implementation of the method for reading 3D NAND flash memory provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0017] Please refer to figure 1 , is a schematic diagram of a storage structure of a 3D NAND according to a specific embodiment of the present invention. Each black dot represents a storage unit.

[0018] The storage structure of the 3D NAND includes a plurality of storage units arranged in an array in a three-dimensional space to form a plurality of storage strings, and the channels of the storage units in the same storage string are physically connected. The transistor at the top of each memory string is an upper selection transistor, which is connected to the bit line, and the transistor at the bottom of each memory string is a lower selection transistor, and different memory strings are distinguished by the upper selection transistor and the lower selection transistor. A plur...

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Abstract

The invention relates to a method for reading 3D NAND flash memory, the 3D NAND flash memory includes a plurality of memory cells arranged in an array within a three-dimensional space, forming a plurality of memory strings, the transistor at the top of each memory string is an upper select transistor, the upper selection tube is connected to a bit line, the transistor at the bottom of the string is a lower select transistor, a plurality of memory cells located within the same layer form a memory row, the gates of the memory cells located in the same memory row are all connected to the same word line, and the memory string in which the memory cells are to be read is taken as a selected string. The reading method is characterized in that the reading method comprises the steps of a preconduction stage and a reading stage, wherein a continuous precharge voltage is applied to the bit line in the preconduction stage; at the same time, the upper selection tube of the selected string and the upper selection tube of the unselected string are turned on, and the lower selection tube of the selected string and the lower selection tube of the unselected string are turned off.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for reading 3D NAND flash memory. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] In the 3D NAND flash memory structure, three-dimensional arrangements are made according to series and rows. In the prior art, when a certain storage unit is read, it often causes read interference to other storage units adjacent to the storage unit, resulting in data drift. [0004] How ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26G11C16/08
CPCG11C16/08G11C16/26
Inventor 刘红涛靳磊黄莹魏文喆王启光
Owner YANGTZE MEMORY TECH CO LTD
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