The invention requests to protect a three-stage comparator system suitable for an ADC (Analog to Digital Converter) with medium and low precision, high speed and low power consumption, which comprises a first-stage four-input two-output dynamic small signal preamplifier, a second-stage two-input two-output dynamic small signal preamplifier and a latch, wherein the dynamic pre-amplifier comprises an input differential pair transistor, a tail charge source and a charge steering branch; the latch includes an input stage, a latch stage, and an output stage. The invention aims to improve all modules in a comparator circuit into a dynamic structure, so that the circuit is in an open-circuit state when no control time sequence is input, quiescent current is eliminated, and the power consumption is further reduced. And on the other hand, the offset voltage of the input end of the comparator is reduced through the gain multiple of the two-stage dynamic preamplifier, so that the precision of the comparator is guaranteed. The innovation point lies in that compared with a traditional architecture, the full-dynamic three-level structure has a remarkable effect of reducing the circuit power consumption and the offset voltage on the basis of the full-dynamic three-level structure.