75results about How to "Increase read current" patented technology

A magnetoresistance effect element is also located between second wiring and common wiring. The magnetoresistance effect element is electrically connected to the second wiring without a spin filter. When a reading current is supplied between the second wiring for supplying a reading current and the common wiring, since this is not supplied via a spin filter, no spin polarized current is supplied into the magnetoresistance effect element, so that it becomes difficult to magnetization-reverse a magnetosensitive layer. Even in a structure where, in order to improve recording density, the magnetosensitive layer is reduced in area so as to lower a writing current, no magnetization reversal occurs due to a supply of the reading current, and information can be read out without making the reading current considerably small in comparison with the writing current.

The embodiment of the invention provides a flash memory unit for a shared source line and a forming method thereof. The provided flash memory unit for the shared source line comprises a semiconductor substrate, a source line, a floating gate dielectric layer, a floating gate, a control gate dielectric layer, a control gate, side wall dielectric layers, side walls, a tunneling oxide layer, a word line, a drain electrode and a source electrode, wherein the source line is positioned on the surface of the semiconductor substrate; the floating gate dielectric layer, the floating gate, the control gate dielectric layer and the control gate are sequentially positioned on the surface of the semiconductor substrate on two sides of the source line; the side wall dielectric layers are positioned between the source line and the floating gate as well we between the source line and the control gate; the side walls are positioned on the floating gate and the control gate, which are far from the source line; the tunneling oxide layer is adjacent to the side wall and is positioned on the surface of the semiconductor substrate; the word line is positioned on the surface of the tunneling oxide layer; the drain electrode is positioned in the semiconductor substrate at one side of the word line, which is far from the source line; the source electrode is positioned in the semiconductor substrate which is right opposite to the source line; and the floating gate is provided with a p-type doping end which is close to the source line, wherein the doping type of the floating gate is in a p type and the doping type of other parts is respectively in an n type.

Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.

A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism. The technique of the present invention provides a particularly simple and power efficient technique for providing such assist mechanisms.

The invention discloses a static random access memory (SRAM) based on a back gate structure of a FDSOI device, all transistors on the novel static random access memory are FDSOI devices, and back gates of the devices are connected with a word line WL. When the SRAM performs read-write operation, the word line is at a high level, so that the threshold voltage of the PMOS is increased, and the threshold voltage of the NMOS is reduced, thereby enhancing the write-in capability of the SRAM and improving the read current; in the maintaining state, the word line WL is at a low level, and the threshold voltage of the device on the SRAM is not different from the threshold voltage of the device on the traditional FDSOI SRAM, so that the static power consumption is not changed.

The invention discloses a three-dimensional NAND ferroelectric memory and a preparation method thereof, and the three-dimensional NAND ferroelectric memory comprises a substrate layer (1), a conductive layer (2) and a stacked layer which are sequentially stacked, and the stacked layer comprising a plurality of isolation layers and a plurality of control gate electrode layers which are stacked; anda plurality of channel groups, each channel group in the plurality of channel groups comprising two channels; the two channels being arranged in a manner of penetrating through the laminated layer; the bottom ends of the two channels being embedded into the conductive layer (2). The bottom ends of the two channels are communicated, a separation layer (6) for separating the control gate electrodelayers of the two channels is arranged between the two channels, and a buffer layer (7), a ferroelectric film layer (8), a channel layer (9) and a channel group (5) formed by connecting a plurality offerroelectric field effect transistors (13) in series are sequentially arranged on the inner walls of the channels. More compact wiring can be obtained through channel group arrangement of the memory, higher-density integration is realized, and the reliability is higher.

The invention discloses a forming method for a memory cell of a flash memory. The forming method comprises the steps of: providing a semiconductor substrate; forming a first insulating layer on the surface of the semiconductor substrate; forming a floating gate polycrystalline silicon layer on the surface of the first insulating layer; forming a stress layer on the surface of the floating gate polycrystalline silicon layer; after the forming of the stress layer, conducting thermal annealing on the stress layer, the floating gate polycrystalline silicon layer, the first insulating layer and the semiconductor substrate; after thermal annealing, removing the stress layer; after the removal of the stress layer, forming a source line layer passing through the floating gate polycrystalline silicon layer and the first insulating layer on the surface of the semiconductor substrate; and removing part of the floating gate polycrystalline silicon layer and forming a floating gate layer on the surface of the first insulating layer on two sides of the source line layer, wherein the floating gate layer is electrically isolated from the source line layer. The forming method for the memory cell of the flash memory can retain stress inside the floating gate layer, thereby enhancing the channel carrier mobility of the memory cell of the flash memory and reducing the size of the memory cell of the flash memory simultaneously when improving the data retention.

The invention discloses a nonvolatile memory, which includes a basement, an active layer, an element isolation layer and a memory cell. The active layer is arranged on the basement and protrudes from the surface of the basement. A plurality of element isolation layers are arranged on both sides of the active layer, and the surface of the element isolation layer is lower than the surface of the active layer. The memory cell comprises a control grid, a charge storage layer, a roof cover layer and a source electrode/drain electrode region. The control grid is arranged on the basement across the active layer. The charge storage layer is arranged on the lateral wall of the active layer and is located between the control grid and the active layer. The roof cover layer is arranged on the top of the active layer and is located between the control grid and the active layer. The source electrode/drain electrode region is arranged in the active layer at the both sides of the control grid.

A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.