Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell

Abstract

The invention relates to a fin field effect transistor memory cell (200), a fin field effect transistor memory cell arrangement, and a method for producing a fin field effect transistor memory cell. Said fin field effect transistor memory cell comprises a first (201) and a second (202) source / drain area and a gate area. The memory cell further comprises a semiconductor fin (204) encompassing the channel zone between the first and the second source / drain area. Also provided is a charge storage layer (207, 208) that is disposed at least in part on the gate area. A wordline area (205, 206) is arranged in at least one sector of the charge storage layer. The charge storage layer is designed such that electric charge carriers can be selectively introduced into or removed from the charge storage layer by applying predefined electrical potentials to the fin field effect transistor memory cell.

Description

technical field [0001] The present invention relates to a FinFET memory cell, a FinFET memory cell configuration and a method for manufacturing a FinFET memory cell. Background technique [0002] Due to the rapid development of computer technology, a high-density, low-power, and non-volatile memory is required, especially for mobile devices for data storage. [0003] A floating gate memory is disclosed in the prior art, in which a conductive floating gate region is disposed on a gate insulating layer of a field effect transistor integrated in a substrate, and the Fuller-Nordham through Tunneling (Fowler-Nordheim Tunneling) can permanently introduce charge carriers into the floating gate region. Due to field effects, the threshold voltage value of such a transistor is related to whether charge carriers are stored in the floating gate, and therefore, items of memory information can be encoded as charge carriers in the floating gate layer existence or non-existence. [0004]...

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Problems solved by technology

[0009] However, the memory cell disclosed in literature [2] also has the disadvantages of low size application flexibility and small read current, especially in the case of a small transistor width

[0010] All in all, the floating gate memory cell has the disadvantage of high voltage, and the continuous access time for each memory cell is not fast enough; the split gate cell has the disadvantage of low size application flexibility, and each Moderate storage density for one bit

According to the literature [2], the disadvantage of the memory cell based on source-side charge carrier injection is that when the channel length is below 200nm, its size application flexibility is low, and in the case of a small transistor width, its The read current is also lower

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