33results about How to "Enhance the performance of anti-total dose radiation" patented technology

The invention provides a total dose radiation resistant strengthening method of a flash memory circuit, which comprises the following steps of: 1, providing a flash memory array and adding a monitoring memory array with a pre-stored logic value of 0 connected to the flash memory array; 2, determining the read voltage of the monitoring memory array; 3, determining a threshold value of a number of monitor memory array cells whose logical value changes to 1; 4, sequentially reading the read data of the monitoring memory array unit and adding the read data under the working state of the flash memory array; 5, comparing the addition result with the quantity threshold value of the monitoring memory array cell, and clearing the addition result when the addition result is less than the quantity threshold value; when the addition result is greater than or equal to the number threshold, refreshing the flash memory array and the monitor memory array. The invention can detect the leakage of the memory array in advance and refresh the memory array in time, thereby improving the total dose radiation resistance of the memory array and ensuring the stability of the device.

The invention discloses a bulk-silicon MOSFET (METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR) structure. The bulk-silicon MOSFET structure comprises a p+ layer (2) and an n- layer (3), wherein the p+ layer (2) and the n- layer (3) are directly contacted; the n- layer is made of wide-bandgap 6H-SiC material. The bulk-silicon MOSFET structure disclosed by the invention has the advantage that the radiation resistance of the bulk-silicon structure is improved. Compared with the SOI (Silicon On Insulator) technology, the bulk-silicon MOSFET structure disclosed by the invention has the beneficial effects that the self-heating effect is improved, the total dosage effect is eliminated, and the cost is reduced.

The invention discloses a manufacture method of a VDMOS device with irradiation resistance. The manufacture method of the VDMOS device is characterized by forming a gate oxide layer, evaporating aluminum on the gate oxide layer, and then diffusing aluminum at high temperature to form a gate medium of an Si-O-Al structure. Positive charges accumulated in the gate medium can be reduced when the VDMOS device is irradiated; the resistance to total dose irradiation of the device is improved; meanwhile, compared with the conventional silicon dioxide gate medium, the gate medium of the Si-O-Al structure is higher in dielectric constant; the resistance to single event gate rupture of the device can be improved. The manufacture method can be used for effectively overcoming the contradiction of requirements on the thickness of the resistance to total dose irradiation and the single event gate rupture and optimizing the resistance to total dose irradiation and the single event gate rupture at the same time; the process is simple; the resistance to the irradiation of the VDMOS device is improved.

The invention provides a VDMOS device with total dose irradiation resistance and a manufacturing method thereof. The device comprises a composite gate oxide layer, a polysilicon gate electrode and anN-epitaxial layer. The composite gate oxide layer comprises a silicon dioxide layer and a silicon nitride layer, and the composite gate oxide layer is between the N-epitaxial layer and the polysilicongate. The present invention provides the VDMOS device with a two-layer composite gate oxide structure and total dose irradiation resistance and the manufacturing method thereof.

The present invention provides a method for hardening anti-total dose radiation of flash memory, which includes: step 1, providing a flash memory storage array, and a monitoring storage array adjacent to the flash memory storage array; step 2, when the flash memory storage array is not working, Close the connection between the flash memory storage array and the peripheral circuit, make the monitoring storage array start to work, and apply a read voltage to the gate of the monitoring array unit; step 3, output the total current of the bit line of the monitoring storage array, and compare it with the reference current threshold Compare; step 4, judge the comparison result, if the total current of the bit line is less than the reference current, read the monitoring storage array again after a fixed time interval; if the total current of the bit line is greater than or equal to the reference current, then read the flash memory storage array and the monitoring storage array Perform a refresh operation. The invention can find electric leakage by monitoring the magnitude of the bit line current of the storage array, and improve the ability of the storage array to resist total dose radiation.

The invention relates to a dielectric isolation structure and a dielectric isolation method for an SOI technology. The isolation structure comprises a P-type substrate, a buried oxide layer, SOI material top silicon, a full dielectric isolation trench, a partial dielectric isolation trench, a linear oxide layer, and an oxide layer or an oxide insulation layer. The full dielectric isolation trench and the partial dielectric isolation trench are disposed inside the SOI material top silicon and above the buried oxide layer. The linear oxide layer is disposed on the inner surfaces of the full dielectric isolation trench and the partial dielectric isolation trench. The oxide layer or the oxide insulation layer is surrounded by the linear oxide layer, and is disposed inside the full dielectric isolation trench and the partial dielectric isolation trench. The linear oxide layer is disposed between the isolation trenches and the SOI material top silicon. The radiation resistance of an integrated circuit is improved. Moreover, the complexity and difficulty of the SOI full dielectric isolation process of a thick silicon film under the process condition of big line width are reduced, the field region and the full-dielectric isolation region are formed at the first attempt, and a smooth silicon surface is ensured.

The invention discloses an integrated circuit for resisting full-scale irradiation of a NMOS component, belonging to the field of electronic technique. The integrated circuit for resisting full-scale irradiation of a NMOS component of the invention comprises a NMOS component and a PMOS component. The components are separated via a tunnel on a substrate. The tunnel is filled with filler materials. In a tunnel adjacent to the NMOS component, a sacrifice material layer is embedded in the filler materials, wherein the sacrifice material is silicon doped with the third main group element. The invention can be applied to the industries relative to full-scale irradiation such as aerospace, military affairs, nuclear power, high energy physics, and the like.

The invention relates to the technical field of power semiconductors, in particular to a junction terminal structure capable of improving the ability to resist total dose radiation. In the present invention, field oxide layers with different thicknesses are mainly arranged on both sides above the field limiting ring, and there are polysilicon field plates on both sides above the ring. Since there is a difference in the thickness of the field oxide layer below the polysilicon field plate, the polysilicon field plates on both sides are vertically There is a height difference, and the staggered polysilicon field plate structure and the field oxide layer structure below form a capacitive structure, and the redistribution weakens the superimposed effect of the electric field formed under the right field plate due to the total dose irradiation, so that The voltage resistance of the junction terminal after the total dose irradiation is improved to a certain extent. On the premise of not increasing the terminal area of ​​the junction, the invention improves the anti-total dose radiation capability of the device, reduces the withstand voltage drop caused by radiation, and satisfies the requirements of high-power and complex environment applications. The invention is particularly applicable to power semiconductor devices.

The invention discloses a novel integrated circuit resisting total dose radiation of N-Metal-Oxide-Semiconductor (NMOS), belonging to the technical field of electronics. The novel integrated circuit resisting total dose radiation of the NMOS comprises an NMOS element and can also comprises a PMOS element, wherein the elements are insulated by a groove on a substrate. The novel integrated circuit resisting total dose radiation of NMOS is characterized in that: in the groove adjacent to the NMOS element, an air interface layer exists between a groove filling material and a substrate material arranged at one side of the groove filling material, and another air interface layer also exists between the groove filling material and a substrate material arranged at the other side of the groove filling material. The air interface layers are formed through etching contact parts among the groove filling material and the substrate materials. The invention can be applied to spaceflight, military area, nuclear power, high energy physics and other industries relevant to total dose radiation.

The present invention provides a flash memory storage circuit anti-total dose effect reinforcement method, comprising: step 1, providing a flash memory storage array; step 2, compiling initial information into coded information, and inputting the flash memory storage array, the binary code in the coded information " The number of "0" and "1" is equal; Step 3, interpret the coding information in the flash memory storage array, and count the number of binary codes "0" and "1" obtained from the interpretation; Step 4, compare the statistical results, When the numbers of the interpreted binary codes "0" and "1" are equal, the coded information is decoded and read; when the interpreted numbers are not equal, the read voltage of the flash storage array is adjusted until the interpreted binary code "" The number of 0" and "1" is equal. The invention can effectively maintain the performance stability of the flash storage circuit by adjusting the reading voltage.

The invention discloses a redundant doping radiation-proof MOS (Metal Oxide Semiconductor) field-effect tube based on a 65nm process, and mainly solves that a traditional 65nm MOS field-effect tube has the problems of threshold voltage drifting, sub-threshold swing degeneration and the degeneration of OFF leakage current under a total dose irradiation environment. The field-effect tube comprises a P-type substrate (1) and epitaxial layers (2) located on a substrate, wherein isolation grooves (3) and grids (6) are respectively arranged all around the upper parts and middle parts of the epitaxial layers, the epitaxial layers between the two side boundaries of a grid and the boundaries in the isolation grooves are internally provided with source and drain active areas (4), and the epitaxial layers below the two side boundaries of the grid are internally provided with light dope source and drain areas (5); a channel is formed in an area between the two light dope source and drain areas (5) is located just below the grid, and a redundant doping areas (7) are inserted in the interfaces of the epitaxial layers at the bottom of the two side isolating grooves which are parallel to the length direction of the channel. According to the MOS field-effect tube provided by the invention, the total dose resistant radiation capacity of devices can be improved, and the field-effect tube can be used for preparing massive integrated circuits.