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CMOS integrated circuit resisting total dose radiation

A total dose irradiation, integrated circuit technology, applied in the field of electronics, can solve the problems of increasing the power consumption of integrated circuits, large off-state leakage current, etc., to improve the total dose resistance performance, eliminate parasitic leakage, and improve the resistance to total dose irradiation. performance effect

Inactive Publication Date: 2012-05-30
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Before the device supervisor is turned on, the supervisor is in the off state, but at this time the parasitic tube has been turned on, resulting in a large off-state leakage current
This off-state leakage current will greatly increase the power consumption of the integrated circuit, and have a relatively large negative impact on the reliability of the integrated circuit, which has become a total dose radiation reliability problem that needs to be solved urgently at this stage.

Method used

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  • CMOS integrated circuit resisting total dose radiation
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  • CMOS integrated circuit resisting total dose radiation

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Embodiment Construction

[0017] The present invention will be further described below through a specific preparation example in conjunction with the accompanying drawings.

[0018] This embodiment prepares the CMOS integrated circuit of the present invention that is resistant to total dose irradiation of NMOS devices, mainly including the following steps:

[0019] 1) Silicon dioxide and silicon nitride formation. Such as figure 2 shown. Thermally oxidize and grow a layer of silicon dioxide with a thickness of about 100 angstroms to 200 angstroms on the bulk silicon substrate 1 as a stress buffer layer 2 between silicon nitride and the silicon substrate, and then use low-pressure chemical vapor deposition (LPCVD) method to deposit a layer of 1000 angstrom to 1500 angstrom silicon nitride as the barrier layer 3 .

[0020] 2) Trench lithography and etching. Such as image 3 As shown, after defining the shown pattern by photolithography, the trapezoidal groove 4 is etched by reactive ion etching (RI...

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Abstract

The invention discloses a CMOS integrated circuit resisting total dose radiation, belonging to the technical field of electronics. The CMOS integrated circuit resisting total dose radiation comprises an NMOS element and a PMOS element which are insulated by a groove. The CMOS integrated circuit resisting total dose radiation is characterized in that the groove is filled with a mixture of a first insulation material and a second insulation material, wherein the first insulation material generates fixed positive charges under the total dose radiation, the second insulation material generates fixed negative charges under the total dose radiation, and the mixture is in weak charges or electric neutrality. The invention can be applied to spaceflight, military, nuclear power, high energy physics and the other industries relevant to total dose radiation.

Description

technical field [0001] The invention relates to a CMOS integrated circuit, in particular to a novel CMOS integrated circuit capable of resisting total dose radiation, which belongs to the field of electronic technology. Background technique [0002] Integrated circuit technology is being more and more widely used in industries related to total dose radiation, such as aerospace, military, nuclear power and high-energy physics. Moreover, with the continuous improvement of the integration level of integrated circuits, the size of semiconductor devices is decreasing day by day. Shallow trench isolation technology is becoming the mainstream technology for electrical isolation between devices in integrated circuits due to its excellent device isolation performance. However, due to the damage of the silicon dioxide oxide layer in the device by the total dose of irradiated particles, a large amount of fixed positive charges will be generated in the oxide layer of the shallow trench ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L23/552H01L21/8238H01L21/76
Inventor 刘文黄如
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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