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New type integrated circuit for resisting full-scale irradiation of NMOS component

A total dose irradiation and integrated circuit technology, applied in the electronic field, can solve the problems of increasing integrated circuit power consumption, large off-state leakage current, etc., achieve simple manufacturing process steps, wide application prospects, and enhance the anti-total dose radiation performance Effect

Inactive Publication Date: 2012-01-18
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Before the device supervisor is turned on, the supervisor is in the off state, but at this time the parasitic tube has been turned on, resulting in a large off-state leakage current
This off-state leakage current will greatly increase the power consumption of the integrated circuit, and have a relatively large negative impact on the reliability of the integrated circuit, which has become a total dose radiation reliability problem that needs to be solved urgently at this stage.

Method used

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  • New type integrated circuit for resisting full-scale irradiation of NMOS component
  • New type integrated circuit for resisting full-scale irradiation of NMOS component
  • New type integrated circuit for resisting full-scale irradiation of NMOS component

Examples

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Embodiment Construction

[0018] The present invention will be further described below through a specific preparation example in conjunction with the accompanying drawings.

[0019] In this embodiment, the integrated circuit prepared according to the total dose irradiation of NMOS devices according to the present invention mainly includes the following steps:

[0020] 1) Formation of silicon dioxide and silicon nitride. Such as image 3 As shown, a layer of silicon dioxide with a thickness of about 100 angstroms to 200 angstroms is grown by thermal oxidation on a silicon substrate 1 as a stress buffer layer 2 between silicon nitride and the silicon substrate, and then a low-pressure chemical vapor phase is used to Deposition (LPCVD) method deposits a layer of 1000 angstrom to 1500 angstrom silicon nitride as the barrier layer 3 .

[0021] 2) Trench lithography and etching. Such as Figure 4 As shown, after the pattern shown is defined by photolithography, the trapezoidal trench 4 is etched between ...

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Abstract

The invention discloses an integrated circuit for resisting full-scale irradiation of a NMOS component, belonging to the field of electronic technique. The integrated circuit for resisting full-scale irradiation of a NMOS component of the invention comprises a NMOS component and a PMOS component. The components are separated via a tunnel on a substrate. The tunnel is filled with filler materials. In a tunnel adjacent to the NMOS component, a sacrifice material layer is embedded in the filler materials, wherein the sacrifice material is silicon doped with the third main group element. The invention can be applied to the industries relative to full-scale irradiation such as aerospace, military affairs, nuclear power, high energy physics, and the like.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to an integrated circuit capable of resisting total dose irradiation of NMOS devices, and belongs to the field of electronic technology. Background technique [0002] Integrated circuit technology is being more and more widely used in industries related to total dose radiation, such as aerospace, military, nuclear power and high-energy physics. Moreover, with the continuous improvement of the integration level of integrated circuits, the size of semiconductor devices is decreasing day by day. Shallow trench isolation technology is becoming the mainstream technology for electrical isolation between devices in integrated circuits due to its excellent device isolation performance. However, due to the damage of the silicon dioxide oxide layer in the device by the total dose of irradiated particles, a large amount of fixed positive charges will be generated in the oxide layer of the shallow trenc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/088H01L27/092H01L23/552H01L21/762
Inventor 刘文黄如王思浩黄德涛王健
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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