A dielectric isolation structure and method for SOI process

Abstract

The invention relates to a dielectric isolation structure and a dielectric isolation method for an SOI technology. The isolation structure comprises a P-type substrate, a buried oxide layer, SOI material top silicon, a full dielectric isolation trench, a partial dielectric isolation trench, a linear oxide layer, and an oxide layer or an oxide insulation layer. The full dielectric isolation trench and the partial dielectric isolation trench are disposed inside the SOI material top silicon and above the buried oxide layer. The linear oxide layer is disposed on the inner surfaces of the full dielectric isolation trench and the partial dielectric isolation trench. The oxide layer or the oxide insulation layer is surrounded by the linear oxide layer, and is disposed inside the full dielectric isolation trench and the partial dielectric isolation trench. The linear oxide layer is disposed between the isolation trenches and the SOI material top silicon. The radiation resistance of an integrated circuit is improved. Moreover, the complexity and difficulty of the SOI full dielectric isolation process of a thick silicon film under the process condition of big line width are reduced, the field region and the full-dielectric isolation region are formed at the first attempt, and a smooth silicon surface is ensured.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a dielectric isolation structure used in SOI technology and a method thereof. Background technique [0002] SOI (Silicon-On-Insulator) technology, as a full-dielectric isolation technology, effectively overcomes the shortage of bulk silicon materials with its unique structure, and fully exploits the potential of silicon integrated circuit technology. Power consumption, high integration and high reliability VLSI mainstream technology. SOI technology adopts full dielectric isolation, which completely eliminates the parasitic latch effect of CMOS devices, reduces single event flipping interfaces, and has excellent anti-single event and instantaneous radiation capabilities, enabling SOI chips to work in the harshest cosmic ray environment , are widely used in space science. However, the charge trapping and interface states generated by the total dose ionization damage in ...

AI Technical Summary

Problems solved by technology

However, for the SOI process with thick silicon film, the full dielectric isolation process between devices is difficult and complex, and the shallow trench isolation technology cannot meet the circuit requirements

Images