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Novel integrated circuit resisting NMOS element total dose radiation

A technology of total dose irradiation and integrated circuits, applied in the field of electronics, can solve the problems of large channel mobility of parasitic tubes, increased power consumption of integrated circuits, leakage current, etc., and achieve simple manufacturing process steps, wide application prospects, enhanced resistance Effect of Total Dose Irradiation Performance

Inactive Publication Date: 2010-03-10
PEKING UNIV
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Before the main tube of the device is turned on, the main tube is in the off state, but at this time the parasitic tube has been turned on, and because the contact quality at the interface between the shallow trench isolation material silicon dioxide and the substrate is very good at this time, there are few interface states , the channel mobility of the parasitic tube is relatively large, and the electron movement speed is relatively fast, which will form a large off-state leakage current
This off-state leakage current will greatly increase the power consumption of the integrated circuit, and have a relatively large negative impact on the reliability of the integrated circuit, which has become a total dose radiation reliability problem that needs to be solved urgently at this stage.

Method used

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  • Novel integrated circuit resisting NMOS element total dose radiation
  • Novel integrated circuit resisting NMOS element total dose radiation
  • Novel integrated circuit resisting NMOS element total dose radiation

Examples

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Embodiment Construction

[0018] The present invention will be further described below through a specific preparation example in conjunction with the accompanying drawings.

[0019] In this embodiment, an integrated circuit for resisting total dose irradiation of NMOS devices based on silicon dioxide material prepared by water vapor oxidation according to the present invention mainly includes the following steps:

[0020] 1) Formation of silicon dioxide and silicon nitride. Such as image 3 As shown, a layer of silicon dioxide with a thickness of about 100 angstroms to 200 angstroms is grown by thermal oxidation on a silicon substrate 1 as a stress buffer layer 2 between silicon nitride and the silicon substrate, and then a low-pressure chemical vapor phase is used to Deposition (LPCVD) method deposits a layer of 1000 angstrom to 1500 angstrom silicon nitride as the barrier layer 3 .

[0021] 2) Trench lithography and etching. Such as Figure 4 As shown, after defining the shown pattern with photol...

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Abstract

The invention discloses a novel integrated circuit resisting NMOS element total dose radiation, belonging to the technical field of electronics. The novel integrated circuit resisting NMOS element total dose radiation comprises an NMOS element and can also comprise a PMOS element, wherein the elements are insulated by a groove on a substrate. The novel integrated circuit resisting NMOS element total dose radiation is characterized in that a silicon dioxide material prepared through steam oxidation exists between a groove filling material and a substrate material in the groove adjacent to the NMOS element. The silicon dioxide prepared through steam oxidation is prepared by the following method: introducing mixed gases of high purity water and oxygen into an interface containing silicon to oxidize the silicon in the interface so as to obtain silicon dioxide. The invention can be applied to spaceflight, military, nuclear power, high energy physics and other industries relevant to total dose radiation.

Description

technical field [0001] The invention relates to integrated circuits, in particular to a novel integrated circuit capable of resisting total dose irradiation of NMOS devices, and belongs to the field of electronic technology. Background technique [0002] Integrated circuit technology is being more and more widely used in industries related to total dose radiation, such as aerospace, military, nuclear power and high-energy physics. Moreover, with the continuous improvement of the integration level of integrated circuits, the size of semiconductor devices is decreasing day by day. Shallow trench isolation technology is becoming the mainstream technology for electrical isolation between devices in integrated circuits due to its excellent device isolation performance. However, due to the damage of the silicon dioxide oxide layer in the device by the total dose of irradiated particles, a large amount of fixed positive charges will be generated in the oxide layer of the shallow tr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/088H01L23/552H01L21/8234H01L21/762H01L21/316
Inventor 刘文黄如
Owner PEKING UNIV
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