The invention concerns a
random access memory cell comprising:at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop,at least a first asymmetric dual-gate access
transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access
transistor (TA1F, TAW1F) disposed respectively between a first
bit line (BLT, WBLT) and a first storage node (T), and between a second
bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access
transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to
route a biasing
signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).