57results about How to "Avoid electric field concentration" patented technology

In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

A trench gate transistor whose gate changes the depth thereof intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The sum of length measurements of the underlying portion of the second offset region measured from the lower corner of the trench in a direction parallel to the substrate and in a direction perpendicular to the substrate is 0.1 μm or greater.

To effectively perform lightning protection in a blade for wind power generation and to prevent the blade from being damaged when arresting lightning. The lightning protection structure of the blade for wind power generation includes a conductive lightning receptor 1 attached to a part of the blade for wind power generation, and a ceramic member 10 interposed between at least surface-layer portions of the lightning receptor 1 and the blade 5. Therefore, an electric field is likely to concentrate at an interface between the ceramic member 10 having excellent heat resistance and the lightning receptor 1, so that it is possible to effectively prevent the blade 5 from being damaged due to a concentration of the electric field at the interface of the blade 5 attached with the lightning receptor 1 when arresting the lightning.

A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the second pillar regions being provided in paired state and alternately, in a device portion and a terminal portion surrounding the device portion, along a surface on the side of a second electrode disposed on the opposite side of the first semiconductor region from the first electrode. The semiconductor device further includes a lateral RESURF (reduced surface field) region of the second conductivity type disposed at a surface portion, on the opposite side from the first semiconductor region, of the second semiconductor region in the terminal portion.

The invention provides a revolving body surface high boss electrolytic machining tool electrode assembly and an electrolytic machining method, and belongs to the technical field of electrolytic machining. The method is characterized in that the tool electrode assembly comprises a tool cathode, a first insulating cavity and a second insulating cavity; and the tool cathode is of a revolving body structure, the surface of the tool cathode is provided with a hollowed-out groove structure, and an opening of the groove structure is of a protruding guide circle structure; the outer side of the firstinsulating cavity is fixedly attached to the inner wall of the protruding guide circular structure, the side wall of the groove structure and the inner side plane of the tool cathode, and the other end of the first insulating cavity is of a tubular structure; the outer side corner of the second insulating cavity is in an arc transition, and the second insulating cavity is fixed in the first insulating cavity through a bottom mounting seat and forms an electrolyte flow channel with the first insulating cavity. According to the method, the electrolyte flowing from the side surface through a first electrolyte inlet can provide a stable flow field for the processing region at the revolving surface, and the electrolyte flowing from the inner side of the groove structure through a second electrolyte inlet can ensure the uniformity of the flow field of the machining region at the side wall of the boss, so that the electrolytic machining stability of the high boss on the surface of the revolving body is ensured.

A metal fitting integration type stress-relief cone is provided with a stress-relief cone which includes a cylindrical rubber-like elastic body on an outer circumference of a cable core and a metal fitting which surrounds the cable core and is integral with a low-voltage side of the stress-relief cone. The stress-relief cone is provided with a cylindrical semi-conducting body part at the low-voltage side and has a bell-mouthed electric-field stress-control part in an end of a high-voltage side, an insulating body part on the high-voltage side with a low-voltage side end concentric with the semi-conducting body part and a cylindrical insulation protective layer which is arranged continuously at the end of the low-voltage side of the insulating body part and is integral with the outer circumference of the semi-conducting body part

The invention discloses a preparation method for a semiconductor device with improved surge current resistance. The semiconductor device is an improved TMBS diode. According to the semiconductor device, metal Cr is utilized to act as an etching mask film to form a deep groove structure on the surface of a SiC drift layer. Wet etching is performed so that line width of the Cr mask film is narrowed, two sides of a mesa which is not etched are exposed to act as an injection mask film to perform Al-ion injection on the surface of the SiC drift layer, and P-type injection regions are formed on the two sides of the mesa. A PN-junction is formed by the injection regions and an N-type drift region. The PN-junction participates in conduction under the condition of high current. The conductance modulation effect is formed by utilizing minority-carrier injection so that the semiconductor device is enabled to have surge current resistance. Besides, a P-injection region can be formed on the bottom part of a groove simultaneously. The bottom part of the groove can be protected by the P-region under the reverse blocking state of the device, the situation that electric field concentration is formed on a non-ideal etching surface can be avoided, early breakdown can be prevented and thus reliability of the device can be enhanced.

A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.

The invention provides a cable connector device, and the device comprises a central connector and two terminal connectors. Two ends of the central connector are correspondingly connected with the twoterminal connectors in a detachable manner. The central connector comprises a connector, two connection sleeves, and two self-locking mechanisms. Two ends of the connector are respectively connected with the two connection sleeves, and the two self-locking mechanisms are respectively disposed on the two connection sleeves, and are used for locking and unlocking the two central connectors. Each terminal connector comprises an insulating part and a terminal housing, wherein the terminal housing is disposed outside the insulating part, and the insulating part is provided with a plugging connection terminal. There is the first distance between each terminal housing and the corresponding plugging connection terminal, and the outer wall, close to one side of the corresponding plugging connectionterminal, of each terminal housing is provided with at least one positioning groove cooperating with the corresponding self-locking mechanism. According to the invention, the device can achieve the quick locking and separation of the central connector and the terminal connectors through the self-locking mechanisms, and improves the cable connection efficiency.

Disclosed is a method of forming an isolation film in a semiconductor device. In the process of forming a stack structure of a pad oxide film and a pad nitride film that expose a semiconductor substrate in an isolation region, protrusions of a tail profile are formed at the bottom sidewalls of the pad nitride film and the pad oxide film adjacent to the surface of the substrate, and top corners of a trench are made rounded using the protrusions as an anti-etch film when the substrate is etched, Therefore, it is possible to prevent concentration of an electric field on the top corners of the trench and prohibit generation of the leakage current. Accordingly, reliability of the process and electrical characteristics of the device could be improved.

A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.