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393 results about "Structure function" patented technology

The structure function (also known as the proton structure function), like the fragmentation function, is a probability density function. It is somewhat analogous to the structure factor in solid-state physics, and the form factor (quantum field theory).

Thinning in package using separation structure as stop

A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.
Owner:INFINEON TECH AG

Methods and Apparatus for Jammable HCI Interfaces

In exemplary implementations of this invention, a jammable structure functions as an HCI interface. A user provides input by changing the shape of a flexible layer of the jammable structure (e.g., by pressing against it or stretching, twisting or bending it) and receives haptic feedback (e.g., varying stiffness). Sensors are used to determine the shape of the flexible layer. The sensors output data that is indicative of electromagnetic waves that have traveled through the jammable media or of electrical or magnetic phenomena that are produced by the waves. For example, visible or infrared light may be shone through a transparent jammable media to the flexible layer and reflect back to a camera. The media may comprise granular particles (e.g., glass beads) and a liquid (e.g., oil) with matching indices of refraction. Or capacitive sensing may be used to detect the shape of the flexible layer.
Owner:MASSACHUSETTS INST OF TECH

Method for predicating surface roughness and surface topography simulation of car milling compound machining

A method for predicating surface roughness and surface topography simulation of a car milling compound machining comprises the following six steps: step one, a modeling of a unified cutter position coordinate model of a whole cutter and an inserted blade cutter; step two, a modeling of the geometrical movement trace of a milling cutter cutting edge; step three, a consideration of influences of the vibration of the cutters to a workpiece surface morphology; step four, a microscopic surface morphology representation method; step five, a car milling compound machining basic structure function; step six, a simulation algorithm example and an orthogonal test method. The method combines the geometrical simulation and the physical simulation together, static and dynamic deformations which are produced when cutters cut under stress are fully considered, models for general car milling compound machining method of any angle are theoretically built, and a surface method of the roughness calculation of the car milling compound machining is deduced. The method for predicating surface roughness and surface topography simulation of the car milling compound machining has good practical values and broad application prospects in the technical field of machinery manufacturing processing.
Owner:BEIHANG UNIV

Chip Guard Ring Including a Through-Substrate Via

At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
Owner:TESSERA INC

Method for determining normal contact rigidity of loaded joint part by considering interaction effect of micro-bulges on rough surfaces

ActiveCN106709207AOvercome the shortcomings of inaccurate calculation resultsScale-independentDesign optimisation/simulationSpecial data processing applicationsRough surfaceNormal load
The invention provides a method for determining normal contact rigidity of a loaded joint part by considering the interaction effect of micro-bulges on rough surfaces. The method comprises the following steps of: measuring microstructure data of contact surfaces, acquiring micro-profile data of contact surfaces of the joint part by using a three-dimensional profile measuring instrument, extracting the position coordinate of each micro-bulge peal in the length direction, and simulating micro-bulge forms of the rough surfaces; building a relation between a normal load and the contact rigidity; computing fractal parameters of the contact surfaces, theoretically computing the extracted data by using a structure function method, and acquiring fractal dimensions and scale coefficients of the surfaces; and according to the above steps, putting each parameter value of the material to finally compute the normal contact rigidity of the joint part. The new method for determining the normal contact rigidity of the joint surfaces provided by the invention overcomes the defect that the traditional method based on a fractal theory is inaccurate in computation result in the case of heavy load, and has the advantages of strong reliability, being close to actual situation, small computation amount and improved computation efficiency.
Owner:NORTHEASTERN UNIV

Method for measuring thermal resistance of multi-layer heat-conducting material

InactiveCN103105410ARealize thermal resistance measurementRealize analysisMaterial thermal analysisNon destructiveHeat conducting
The invention discloses a method for measuring the thermal resistance of a multi-layer heat-conducting material, which relates to the field of testing, and can be used for measuring the thermal resistance of each material layer in the multi-layer heat-conducting material. A semiconductor device in a testing system has a heat source function and a testing function. The method comprises the following steps of: fixing the semiconductor device on the upper surface of the multi-layer heat-conducting material, and fixing the lower surface of the multi-layer heat-conducting material on a constant temperature platform; and applying operating current to the semiconductor device for a period of time at any moment, removing the operating current after a steady state is achieved, and measuring a change curve of the junction temperature of the semiconductor device along with the time under the testing current. Because the thermal resistance, thermal capacity and heat transfer rate of each material layer in the multi-layer heat-conducting material are different, the thermal resistance and thermal capacity of each heat-conducting material layer are reflected through the measured change curve of the junction temperature of the semiconductor device along with the time; and according to a structure function method, the thermal resistance composition in each material layer in the multi-layer heat-conducting material is calculated. Moreover, the method belongs to non-destructive testing.
Owner:BEIJING UNIV OF TECH

Population distribution spatial-temporal evolution and cognition considering urban pattern characteristics

The invention relates to a population distribution spatial-temporal evolution and cognition method considering urban pattern characteristics. The population distribution spatial-temporal evolution andcognition method comprises the following steps: 1) carrying out scale conversion of multi-source and multi-scale remote sensing images; 2) extracting urban information based on the multi-source remote sensing image; 3) analyzing a multi-scale urban pattern-structure-function spatial-temporal relationship; 4) carrying out spatial-temporal correlation and coupling analysis on population distribution and urban characteristics; 5) constructing a population distribution simulation and prediction system considering urban pattern characteristics; and 6) carrying out spatial-temporal monitoring and cognition on population distribution in different scenes. The population distribution spatial-temporal evolution and cognition method has the advantages that population general survey and statistical data, multi-scale remote sensing data and multi-source land utilization / coverage data are used as data sources; the spatial-temporal characteristics and the evolution rule of the multi-scale urban spatial pattern are studied, and the population distribution spatial-temporal evolution model considering the town characteristic pattern is constructed, and the boundary of the population distribution density is finely described from the multi-level spatial scale, and a theoretical basis and a technical support are provided for population resource utilization and policy adjustment and social and economic resource allocation.
Owner:NANJING FORESTRY UNIV

Natural plant freshness preserving agent for lichee and longan and its use

The present invention discloses natural plant freshness preserving agent for lichee and longan. Various effective components are extracted from several kinds of plant to constitute with the peel and pulp of lichee and longan the so-called structure-function relationship, so as to reach the effects of strengthening the activity of fruit cell, fixig the color, sterilizing, antisepticising and preventing cell void chocking for preservation. The natural plant freshness preserving agent is green, and has no environmental pollution, low cost and high preserving effect.
Owner:WUHUA COUNTY SUPPLY & MARKETING GROUP GUANGDONG PROV

Method and system for predicting junction temperature of power device

ActiveCN107315877AAccurately Predict Junction TemperatureAccurately Characterize Thermal Distribution PropertiesDesign optimisation/simulationSpecial data processing applicationsPower semiconductor deviceSemiconductor chip
The invention discloses a method and a system for predicting a junction temperature of a power device. The method comprises the steps of obtaining an integral structure function curve of a tested device; determining a first chip layer according to a packaging form, a packaging material and a starting point of the integral structure function curve of the tested device; performing layering on the first chip layer according to a slope of a curve segment corresponding to the first chip layer in the integral structure function curve to obtain thermal equivalent layers and corresponding thermal resistance values; and building a thermal equivalent layering model of the chip layer of the tested device according to the thermal equivalent layers and the corresponding thermal resistance values, thereby predicting the junction temperature of the tested device. The thermal equivalent layering model is built for the chip layer by adopting a thermal equivalent layering structure instead of physical layering, so that the thermal equivalent layering model can accurately represent a thermal distribution characteristic of the chip layer in the power semiconductor device; the model can accurately predict the junction temperature of the power device; and the method for building the thermal equivalent layering model is used for all power semiconductor chips, and is convenient to implement and popularize.
Owner:NORTH CHINA ELECTRIC POWER UNIV (BAODING)

Power MOS device temperature rise and thermal resistance component test device and method

The invention relates to a power MOS device temperature rise and thermal resistance component test device and method and belongs to the power MOS device reliability design and test field. According to the test device and method of the invention, a fast switching switch of drain-source voltage and gate-source voltage signal control of a tested power MOS device and a fast switching switch of drain-source high-current work are designed; and an FPGA is adopted to design the acquisition and setting function of drain-source voltage, gate-source voltage and drain-source current. In a testing process, a temperature-sensitive parameter curve is obtained at first; operating current is applied to the device, so that the temperature of the device can rise; after the output power of the device achieves a steady state, the operating current is cut off, and test current is switched on; the junction voltage of the drain-source parasitic diode of the power MOS device is acquired, so that the junction temperature curve of the device can be obtained correspondingly; processing analysis is carried out through adopting a structural function method, so that the thermal resistance components of the power MOS device can be obtained. With the power MOS device temperature rise and thermal resistance component test device and method of the invention adopted, the problems of high prices of test instruments, complicated operation of measurement technologies and long measurement period can be solved.
Owner:BEIJING UNIV OF TECH
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