The invention belongs to the field of reliable computing technologies and particularly relates to a low-complexity and extensible fault-tolerant routing algorithm for a network on chip. The routing algorithm adopts strategies of system partition and divide-and-conquer, and can better tolerate faults occurred in different parts of a central zone, four boundaries and four corner parts. Under the circumstance of certain nodes fault, the entire system can still work, thereby the fault-tolerant capability and the continuous service capability of the system are greatly enhanced, the yield of chips and the service life of the system are improved in a disguised form, and the cost of the system is reduced. The routing algorithm is applicable to occasions having extremely high requirement on reliability, such as aerospace, military network, financial transactions, banks and other key fields as well as the fields, such as civilian use, consumer electronics, and the like.