37 results about "Pseudo randomness" patented technology

The invention provides a digital image encryption method based on a chaotic system and a nucleic acid sequence database. The chaotic map index sequence is used to scramble image pixel positions; Operation; base substitution is performed on the DNA-encoded pixels according to the quaternary hyperchaotic sequence generated by the hyperchaotic Chen system, and its confusion and diffusion properties are further enhanced through ciphertext feedback and chaotic system iteration. The invention relies on the sensitivity and pseudo-randomness of chaotic mapping to initial conditions, combined with the inherent spatial configuration and unique information processing capability of DNA molecules, by using the difference between two chaotic sequences, DNA sequence libraries and the gray value of its own pixel. The transformation and operation of the digital image achieve the purpose of confusion and diffusion, so as to realize the encryption of the digital image. Experimental results show that the invention has large key space and strong sensitivity to keys, and can effectively resist attack operations such as statistical analysis and exhaustive analysis.

The invention discloses a light DFT-S-OFDM secure transmission system based on a digital chaos. The system comprises three encryption steps all together, i.e., insertion of an OFDM synchronous training sequence, DFT matrix signal preprocessing and subcarrier mapping, wherein an OFDM synchronous training sequence and a subcarrier mapping mode are both generated by a chaotic system, DFT matrix element parameters m and n are generated by the chaotic system, by use of initial value sensitivity and pseudo randomness of the digital chaos, encryption processing is performed on DFT-S-OFDM signals, and thus secret transmission is realized. On one hand, since a security system secret key space is huge, the security of high-speed information transmission can be effectively enhanced, and at the same time, since a DFT matrix can substantially reduce a peak average power ratio (PAPR) of OFDM signals, the performance of the transmission system is also improved; and on the other hand, since multiple iteration optimization and multiple discrete Fourier transformation operation are unnecessary in a DFT matrix signal processing system, the whole system has the following advantages: the system architecture is simple, the calculation amount is small, the transceiver cost is low, and transmission of sideband information is unnecessary.

The invention proposes an incoherent frequency compensation and demodulation method and a demodulation device which have low power consumption, high performance and use the pseudo-randomness of the received signal phase and the PN code to realize the wireless digital communication data demodulation which has short distance, low power consumption and low packet loss rate through the carrier frequency error compensation and data recovery; the demodulation device is composed of a digital low-converter, a channel filter, a phase arithmetic unit, a phase differentiator, a frequency compensator and a PN code de-spreading correlator; the intermediate signal is converted into the plural baseband signals which are processed with channel outer band noise filtration so that the amplitude-time signal is converted into the phase-time signal; the phase differentiator is adopted to differentiate the phase-time signal; the frequency compensation circuit compensate the carrier frequency according to the phase difference signal and the phase average signal; the carrier frequency and the phase recovery circuit are avoided; the PN code correlator group processes the matching demodulation towards the semi-cosine shaping 0QPSK and MSK signals of the DSSS directly to recover the baseband data; the incoherent frequency compensation and demodulation method and the demodulation device has the advantages of simple circuit, less quantity of hardware, easy low power consumption integration, good demodulation performance and being applicable to the wireless satellite navigation and the short-range wireless communication device with batteries as the power supply.

The application relates to a radar signal optimization method, device, computer equipment and storage medium. The method utilizes the initial value sensitivity and pseudo-randomness of chaotic coding, and optimizes the key parameters of the signal waveform by reducing the correlation between adjacent pulse signals. : The number of subcarriers, the number of chips, and the initial value of chaos, etc., and then obtain the radar pulse signal combination method with the best anti-replication and forwarding interference performance. And copied the signal pulse, but the process of identification and copying takes a certain amount of time, and the matching gain cannot be obtained with the subsequent pulse, so it has an excellent ability to resist copying and forwarding interference. This method adopts the waveform optimization method to improve the anti-replication and forwarding interference performance of the radar, does not require additional calculations during signal processing, and is more suitable for engineering applications.

The invention discloses a chaotic encryption method for voice information. The method is characterized in comprising the steps of 1), establishing a dynamic variable parameter composite chaotic system and generating a real-value chaotic sequence of which length is the same to that of a plaintext voice sequence through utilization of the system; 2), carrying out binarization processing on the real-value chaotic sequence, thereby obtaining a chaotic key sequence of which length is the same to that of the plaintext voice sequence; and 3), through combination of the chaotic key sequence, carrying out bit-by-bit exclusive or operation on the plaintext voice sequence, thereby obtaining a ciphertext. According to the method, under limited calculation precision, the chaotic sequence with good pseudo-randomness can be generated, the valid precision effect is reduced, and a chaotic sequence cycle is prolonged; and through adoption of a chaotic system cascading mode, the encryption security is improved, a sufficient key space can be generated, and an exhaustive attack can be resisted effectively.

The invention discloses a multisource input true random number generator circuit structure. Multiple noise generating circuits of different types are used as noise sources; with input selection of an option switch, the noise is input into a sampling correcting circuit; on one hand, the input result enters into an output processing module, and on the other hand, the input result enters into a random number counter; the random number counter counts the generated random number, and feeds back the output result to the option switch; then the signals are randomly selected from the multiple noise generating circuits and then output. In the process, due to the randomness of selection from the multiple noise sources, the randomness of the sampling correcting output, and the randomness of application of the random number counter, the pseudo-randomness generated by the original single noise generating circuit due to long-time working can be eliminated wholly. Proved by the theory and experiments, the true random number generator utilizes multiple noise sources and the random number counter to realize feedback, so that the randomness of the long-range data is better than the original random number generator realized by the single noise source.

The invention discloses a cross-memory pseudo-random mapping method for parallel computing. The pseudo-random sequence generated by the maximum sequence code (m-sequence) is used to form an address mapping matrix, which can improve the performance of parallel access and parallel computing, and slow down Store latency in dynamic memory. The present invention adopts an H matrix adjustment method of address mapping, overcomes the weakness of the previous method, and ensures that the same H matrix can be used for forward mapping and reverse mapping. The address mapping matrix generated by the invention is combined with the XOR function to form an address mapping circuit, which is easy to design and simple in structure. For different address widths, the present invention uses an address division mapping method to optimize the pseudo-randomness of the mapping matrix to improve parallel storage performance.

The invention relates to the technical field of circuits and discloses a true random number generator. The true random number generator comprises a random signal generation source circuit, a true random number generation circuit, a PRNG (pseudo random number generator) and a random number interceptor, wherein the random signal generation source circuit is used for generating random number generation source signals; the true random number generation circuit is used for sampling and diffusing the random number generation source signals and a true random number sequence is obtained; the PRNG is used for outputting the serial or parallel random number sequence according to the input true random number sequence; the random number interceptor is used for intercepting the random number sequence of the preset length from the random number sequence output from the PRNG according to the input true random number sequence and feeding back the intercepted random number sequence to the random signal generation source circuit; the random signal generation source circuit is used for adjusting the random number generation source signals according to the random number sequence fed back by the random number interceptor. The true random number generator can be realized through an ordinary logic device, the circuit structure is simple, the true random number generator is independent of the process and has good reusability, and a feedback mechanism is added, therefore, pseudo-randomness due to long-time working without feedback can be eliminated.