Lightweight key sequence generator based on chaotic system and FPGA

A sequence generator and chaotic system technology, which is applied in secure communication and key distribution through chaotic signals, can solve the problems of precision limitation, poor pseudo-randomness of chaotic sequence, low security of chaotic system, etc., and achieve good security and small code size , the effect of less hardware resources

Inactive Publication Date: 2021-01-22
HEILONGJIANG UNIV
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  • Summary
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  • Description
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Problems solved by technology

[0004] In order to avoid the precision limitation of the digital chaotic system implemented by hardware, resulting in poor pseudo-randomness of the chaotic sequence and low security of the chaotic system, when designing the chaotic system, it will be expressed with a larger bit width as much as possible, but this requires a lot of Hardware resources, that is, the accuracy of the chaotic system is limited by hardware resources

Method used

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  • Lightweight key sequence generator based on chaotic system and FPGA
  • Lightweight key sequence generator based on chaotic system and FPGA
  • Lightweight key sequence generator based on chaotic system and FPGA

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Experimental program
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Effect test

Embodiment 1

[0046] A lightweight key sequence generator based on chaotic system and FPGA, including sequence generator module L_chaos based on Logistic chaotic system, 2 nonlinear shift registers NFSR_1 and NFSR_2, data selection C1, C2 and C3 modules, filtering The function H module and the output function Z module are implemented as follows:

[0047] Sequence generator module L_chaos based on Logistic chaotic system

[0048] The implementation of the Logistic chaotic sequence is relatively simple and consumes relatively few hardware resources, so the chaotic sequence is selected as the perturbation and confusion module of the whole system in this key sequence. After initialization and digitization, a digital chaotic system of unsigned fixed-point numbers with a bit width of 20 bits is realized, and the 4th, 6th, 7th, 9th, 11th and 12th bits of the generated chaotic sequence, namely l i+4 , l i+6 , l i+7 , l i+9 , l i+11 and l i+12 It is extracted separately for the data selection ...

Embodiment 2

[0083] System testing and security analysis

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Abstract

The invention provides a lightweight key sequence generator based on a chaotic system and an FPGA, and solves the problem that the precision of the chaotic system is limited by hardware resources. Thelightweight key sequence generator comprises a sequence generator module based on a Logistic chaotic system, two nonlinear shift registers, three data selection modules, a filter function H module and an output function Z module. According to the lightweight key sequence generator, a Logistic chaotic sequence is digitalized and is combined with a nonlinear feedback shift register through a certain algorithm; the chaotic system and the non-linear feedback shift register are well combined, and the FPGA-based hardware implementation ensures the pseudo-randomness of the sequence and the securityof the system, enables the code scale to be smaller, and occupies less hardware resources.

Description

technical field [0001] The invention belongs to the field of information security hardware system encryption, in particular to a light-weight key sequence generator based on a chaotic system and FPGA. Background technique [0002] In the prior art, the lightweight sequence cipher based on FPGA basically adopts traditional nonlinear feedback shift register (NFSR) and linear feedback shift register (LFSR) to realize; combined, [0003] Chaotic systems have many advantages such as initial value sensitivity, unpredictability, fractal properties, and universality. The digitized chaotic sequence also continues the advantages of the chaotic system to a certain extent, so it is especially suitable for encryption systems. With the development of society, lightweight serial ciphers emerge as the times require, which are suitable for applications in resource-constrained devices. [0004] In order to avoid the precision limitation of the digital chaotic system implemented by hardware...

Claims

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Application Information

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IPC IPC(8): H04L9/08H04L9/00
CPCH04L9/0861H04L9/001
Inventor 丁群丁丽娜闫文浩
Owner HEILONGJIANG UNIV
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