74 results about "Process architecture" patented technology

A systems and process architecture which mandates, automates and manages network security and authorization for Internet broadband provider broadband modems and their customer's connectable host device(s), and provides and facilitates real-time automation of service order fulfillment and account processing. An Internet broadband IPsec, PKC, and QoS systems and process architecture which mandates, automates, and manages IPsec, PKC, and QoS for Internet broadband provider broadband modems and their customer's connectable host device(s). A systems and process architecture for determining broadband customer type including one of new, expired, roaming and current.

A computer program product for creating an enterprise management dashboard program, and comprising a process architecture server, a process architect client, a stakeholder client, and/or a process object server. The process architecture server includes a compiler characterized by an access control subsystem (receives role-base access control definition data), a work flow modeling subsystem (receives process model definition data), a data management subsystem (receives data structure definition data), a communication subsystem (receives communication protocol definition data), and a report management subsystem (receives report content definition data). The compiler uses the aforementioned data to create executable computer code for the enterprise management dashboard program based on modeling constructs including project sites, task pages, interface templates, report templates, and/or third-party process content. The resultant enterprise management dashboard program may be used to create and save process objects such as projects, tasks, artifacts (e.g., digital files), and process metrics.

In a network termination device integrated circuit in a point-to-multipoint network, a receiver receives a downstream transmission from a line termination unit within the point-to-multipoint network, a transmitter transmits an upstream transmission to the line termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the downstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the upstream transmission. The downstream transmission is an downstream transmission convergence frame format having an overhead field and a payload field, and the upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field.

A receive system providing enhanced directivity in the form of a narrowed receive beam and a relatively small antenna with performance comparable to a much larger antenna at similar frequencies. Received signals are converted to digital values and stored in a manner which enables subsequent processing directed to improving the resolution of the received signals and to reduce the associated noise corresponding to the received data samples. The Signal-to-Noise ratio of the received data signals is improved as a result of processing techniques made possible by the configuration of the antenna and the digitally stored nature of the received data.

The disclosure relates to a back channel etching oxide thin film transisto process architecture. A method for fabricating a back channel etching (BCE) oxide thin film transistor (TFT) for a liquid crystal display is provided. The method includes forming a first metal layer having a first portion and a second portion over a substrate, depositing a gate insulator over the first metal layer, and disposing a semiconductor layer over the gate insulator. The method also includes depositing a half-tone photoresist to cover a first portion of the semiconductor layer and the first portion of the first metal layer. The half-tone photoresist has a first portion and a second portion thicker than the first portion. The first portion has a through hole above the second portion of the first metal layer. The second portion of the half-tone photoresist covers the first portion of the first metal layer. The method further includes etching a portion of the gate insulator through the via hole such that the second portion of the first metal layer is exposed, removing the first portion of the half-tone photoresist while remaining the second portion of the half-tone photoresist, and etching to remove a second portion of the semiconductor layer that is not covered by the half-tone photoresist.

Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

The invention discloses a dialogue process customization method and a device. In the dialogue process customization method, a dialogue resource customization request is acquired by a customization server, a target dialogue resource from a pre-configured dialogue resource library is determined according to dialogue resource customization information, and then the target dialogue resource is sent, so that a customization client can configure the target dialogue resource into a dialogue process architecture to determine a dialogue process. By means of the dialogue process customization method, non-professional users can customize the dialogue process more freely, and the dialogue process customization method can be suitable for numerous dialogue customizing scenes.

An embodiment of the invention provides an offline test method and device based on a PowerPC multi-core processor. The method includes determining a target program to be tested when the PowerPC multi-core processor is in the multi-core multi-process running state and needs to be tested off line; loading a test task for the target program; extracting a test case from the target program; executing the test case using a simulation interface; ending and deleting the test task when the test case is executed. The method solves the problem in the prior art that software compiling loading consumes long time and the multi-core multi-process timing sequence cannot be simulated or tested due to the fact that repeated compiling, linking and loading of the program must be performed when the test case not passed is executed singly. The working efficiency of an embedded program system is improved in the multi-core multi-process architecture mode, and the completeness and the reliability of the test are also ensured.

The invention discloses a method and a device for carrying out sound control in a browser. The method comprises the following steps that: a sound control switch parameter for carrying out sharing among different processes is arranged in the browser; the sound control switch parameter is subjected to on/off setting; according to the types of playing elements in a web page opened in each process of the browser, an in-process sound control mode and/or an out-of-process sound control mode adopted by the web page in each process are/is determined; and the playing sound of the web page in each process is subjected to on/off operation according to the determined in-process sound control mode and/or the out-of-process sound control mode. The invention provides a solution for carrying out the sound control on the browser of a multi-process architecture; the simultaneous control on the playing sound of a plurality of processes of the browser is realized; and the playing sound in browser framework processes or browser web page processes can be subjected to on/off operation at any time.

A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

An electrical computer system processing architecture for providing fairness amongst client computers of the computer system is disclosed. The electrical computer system processing architecture comprises a plurality of client computers connected to at least one server by a computer network. Each of the client computers is configured to provide requests to the at least one server. The or each server comprises a store for storing requests provided by the plurality of client computers. The or each server is configured to: match complementary requests from the plurality of client computers stored in the store; following matching of complementary requests, assign an indication of how well the requests have been met compared to requests of other client computers of the computer system; accumulate the indications to form an accumulation of indications; and when the accumulation exceeds a predetermined threshold, match future requests in favour of the client computer whose requests have not been met as favourably with requests of other client computers of the computer system, thereby providing fairness amongst client computers of the computer system.