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Offline test method and device based on PowerPC multi-core processor

A multi-core processor and processing tool technology, applied in the computer field, can solve the problems of prolonged test time, long time consumption, large amount of code, etc., and achieve the effect of ensuring completeness

Active Publication Date: 2018-09-25
DATANG MOBILE COMM EQUIP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Judging from the process plan of using the existing technology to implement offline testing of the program, the test of the startup program must go through the stages of compilation, linking, loading and running. If you want to target a failed test after executing multiple use cases If a use case is executed separately, it must go through the stages of "compiling, linking, loading and running" again. For a complete embedded real-time program system, the amount of code is generally relatively large, and it has to go through the stages of compiling, linking, loading and so on. It may take a long time, thereby prolonging the test time and increasing manpower input, which ultimately leads to low test efficiency

Method used

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  • Offline test method and device based on PowerPC multi-core processor
  • Offline test method and device based on PowerPC multi-core processor
  • Offline test method and device based on PowerPC multi-core processor

Examples

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Embodiment 1

[0067] refer to figure 2 , shows a flow chart of the steps of an embodiment of an off-line testing method based on a PowerPC multi-core processor of the present invention, specifically may include the following steps:

[0068] Step 201, when the PowerPC multi-core processor is in a multi-core multi-process running state and needs to be tested offline, determine the target program to be tested;

[0069] In practical applications, the embodiment of the present invention can be applied to an embedded real-time communication system program platform with multi-core and multi-process concurrent processing, and this technology can relate to many fields such as communication, transportation, home appliances, and medical care.

[0070] In a specific implementation, the embodiment of the present invention can determine the target program to be tested when the PowerPC multi-core processor is in the running state of multi-core and multi-process and offline testing is required.

[0071] ...

Embodiment 2

[0095] refer to image 3 , showing a block diagram of the present invention based on a PowerPC multi-core processor offline test device embodiment, specifically may include the following modules:

[0096] The software code module 301 is used to determine the target program to be tested when the PowerPC multi-core processor is in the running state of multi-core and multi-process and needs to carry out offline testing;

[0097] A test module 302, the test module 302 may also include a test loading submodule 3021, a test execution submodule 3022, and a test reset submodule 3033; wherein,

[0098] The test loading submodule 3021 is configured to load a test task for the target program;

[0099] The test execution sub-module 3022 is configured to extract test cases from the target program, and execute the test cases by using the simulation interface;

[0100] The test reset submodule 3023 is configured to end and delete the test task when the test case is executed.

[0101] In a...

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Abstract

An embodiment of the invention provides an offline test method and device based on a PowerPC multi-core processor. The method includes determining a target program to be tested when the PowerPC multi-core processor is in the multi-core multi-process running state and needs to be tested off line; loading a test task for the target program; extracting a test case from the target program; executing the test case using a simulation interface; ending and deleting the test task when the test case is executed. The method solves the problem in the prior art that software compiling loading consumes long time and the multi-core multi-process timing sequence cannot be simulated or tested due to the fact that repeated compiling, linking and loading of the program must be performed when the test case not passed is executed singly. The working efficiency of an embedded program system is improved in the multi-core multi-process architecture mode, and the completeness and the reliability of the test are also ensured.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to an off-line testing method based on a PowerPC multi-core processor and an off-line testing device based on a PowerPC multi-core processor. Background technique [0002] With the rapid development of embedded technology, the demand for embedded processing is also growing rapidly. Today, with the rapid development of integrated circuit technology, the performance of single-core processors has developed to a relatively high level. It is not enough to improve the real-time performance of the system, and the system architecture is developing towards the direction of multi-processor design to solve the problems of high complexity and insufficient computing power of single-processor systems, especially like PowerPC multi-core processors. The CPU of the simplified instruction set architecture performs well in information processing technology in various fields, and thus is favored by t...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F11/26G06F11/263
CPCG06F11/2242G06F11/2273G06F11/261G06F11/263
Inventor 李国静
Owner DATANG MOBILE COMM EQUIP CO LTD
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