The exemplary embodiments provide a reconfigurable
integrated circuit architecture having a predetermined, unit timing increment (or
delay) for both
data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect
bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and
control circuit, with the element interface and
control circuit comprising an input
queue and an output
queue. Each cluster
queue comprises an element interface and control having an input queue and an output queue. The full interconnect
bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect
bus, is completed within a predetermined unit time
delay which is independent of application placement and application data routing on the reconfigurable IC.