Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules

Abstract

The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a conversion of and claims priority to: (1) Kelem, Steven Hennick et al., U.S. Provisional Patent Application Ser. No. 61 / 376,615, filed Aug. 24, 2010, entitled “Hierarchically Scalable Reconfigurable DDM Architecture With Unit-Delay Modules”; (2) Kelem, Steven Hennick et al., U.S. Provisional Patent Application Ser. No. 61 / 376,659, filed Aug. 24, 2010, entitled “Hierarchically Extensible Reconfigurable Zones in a Resilient Device Architecture”; (3) Kelem, Steven Hennick et al., U.S. Provisional Patent Application Ser. No. 61 / 376,662, filed Aug. 24, 2010, entitled “Multi-Context Memory Management Unit”; (4) Kelem, Steven Hennick et al., U.S. Provisional Patent Application Ser. No. 61 / 376,666, filed Aug. 24, 2010, entitled “On-Chip Configuration”; and (5) Kelem, Steven Hennick et al., U.S. Provisional Patent Application Ser. No. 61 / 376,672, filed Aug. 24, 2010, entitled “Data-Driven Integrated Circuit Architecture”; whi...

AI Technical Summary

Benefits of technology

[0020]Exemplary embodiments are also illustrated for configurable memory control which allows multi-threaded and multi-context execution, allowing multiple concurrent read and write operations directly from a configurable full interconnect communication channel.

[0021]Exemplary embodiments also provide an integrated circuit architecture which is capable of significant resiliency, without otherwise unused redundancy. The exemplary IC embodiment may be adapted on an ongoing basis, as may be necessary in the event of a defect, or as may be desirable for incorporation of a new program or function. For example, in the event a defect arises, functionality may be transferred to an unaffected region in real-time or near-real time. The exemplary architecture and software for the IC also allows such transferable functionality, without requiring the entire program to be transferred to a completely redundant processor or otherwise unused computational block. In addition, the exemplary IC embodiments provide for a graceful degradation and notification with increasing defects or problems, which may occur during use (in addition to fabrication), rather than a catastrophic failure.

Problems solved by technology

The process for creating the configurations for the gate arrays of FPGAs is comparatively slow, especially so for determining whether any given configuration meets timing requirements, so that FPGAs generally have not been capable of real-time reconfiguration for immediate changes in functionality, as such timing cannot be guaranteed.

While these large-scale configurable logic elements provide extremely capable acceleration, each group of configurable logic elements is typically different and requires separate programming to carry out its functions.

In addition, such large-scale configurable logic elements are not translatable to other functions, exhibiting similar constraints of application-specific ICs (“ASICs”).

For example, in memory ICs, extra or redundant rows and columns are fabricated; when subsequent testing may reveal that selected rows and columns have defects, those affected IC regions are disabled, with the balance of the memory IC being useable potentially and, with the redundancy, may still meet the memory capacity specification.

These other configurable architectures also do not scale well, for a variety of reasons.

In some instances, interior regions of the IC become starved for resources, as the exterior regions consume all of the input / output (I / O) capability.

In other instances, communication within the IC becomes problematic.

These configurable architectures may also exhibit timing unpredictability and a corresponding inability to provide a timing closure.

For example, recompiling the same netlist may result in different timing delays.

Accordingly, a system designer may not be able to know in advance if a particular mapping, placement and routing will meet system requirements until the mapping, placement and routing has been performed, which is a very time-consuming process with high configuration variability.

In addition, after configuration and during operation, such FPGAs, ASICs, processors, and other configurable logic do not exhibit resiliency.

For example, if a portion of the IC becomes defective during operation, the entire IC fails instantly, losing all functionality.

While the IC may be taken off line or removed, diagnosed, and depending upon the damage, possibly reconfigured, such ICs are not capable of real-time reconfiguration and transferring of functionality to unaffected portions of the IC.

These known technologies, however, do not address the increasing number of defects which are now arising in sub-100 nm IC fabrication.

More particularly, as IC feature size continues to decrease below 90 nm, there are increasing levels of defects and decreased IC yields.

In addition, while an IC initially may be sufficiently free of defects to operate for its intended use, the smaller feature size also increases the probability of IC failure during operation, such as due to tunneling and electromigration effects.

In addition, while each of these prior art technologies have their own advantages, such as an ability to correct design flaws and to work-around minor fabrication defects, none of these prior art technologies provide sustainable resiliency over time, during IC operation.

Whether defects were created during fabrication or much later, during IC usage, these known technologies simply cannot accommodate both certain kinds of defects and certain levels of defects, and the entire IC fails completely.

Such failure is often catastrophic, such that the entire IC fails instantly and without warning.

For example, if a region of a microprocessor fails, the entire microprocessor becomes instantly useless.

In these circumstances, however, either the redundant processor was previously completely idle and unused, or its prior functioning has been superseded and completely lost.

In either event, this resiliency is at the expense of approximately twice the IC area and significantly increased manufacturing costs.

In addition, such basic redundancy efforts do not account for defects which may occur within all redundant components, as even small defects may cause such components to fail.

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