825 results about "Defect free" patented technology

Scanning Laser Epitaxy (SLE) is a layer-by-layer additive manufacturing process that allows for the fabrication of three-dimensional objects with specified microstructure through the controlled melting and re-solidification of a metal powders placed atop a base substrate. SLE can be used to repair single crystal (SX) turbine airfoils, for example, as well as the manufacture functionally graded turbine components. The SLE process is capable of creating equiaxed, directionally solidified, and SX structures. Real-time feedback control schemes based upon an offline model can be used both to create specified defect free microstructures and to improve the repeatability of the process. Control schemes can be used based upon temperature data feedback provided at high frame rate by a thermal imaging camera as well as a melt-pool viewing video microscope. A real-time control scheme can deliver the capability of creating engine ready net shape turbine components from raw powder material.

A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.

Embodiments of methods and an apparatus for utilizing a directed self-assembly (DSA) process on block copolymers (BCPs) to form a defect-free photoresist layer for feature transfer onto a substrate are provided. In one embodiment, a method for performing a dry development process includes transferring a substrate having a layer of block copolymers disposed thereon into an etching processing chamber, wherein at least a first type and a second type of polymers comprising the block copolymers are aggregated into a first group of regions and a second group of regions on the substrate, supplying an etching gas mixture including at least a carbon containing gas into the etching processing chamber, and predominately etching the second type of the polymers disposed on the second groups of regions on the substrate in the presence of the etching gas mixture.

An apparatus and method are disclosed for detecting flaws in electrically conductive materials by observing properties of the back-EMF of the eddy current field generated by driving magnetic flux through the object to be examined. The input signal may include sweeps at several frequencies, and may do so at one time under the principle of wave superposition. The sectorial observations of eddy currents summations may be compared to a known datum for a defect free material, the presence of anomalies in eddy field back EMF divergence tending to provide an indication of an irregularity in the underlying eddy field, and hence in the underlying material itself. The portable unit may have a number of different configurations depending on the nature of the object to be examined, be it a flat or large radius plate, a flange, a rail, or some other structural element.

An image processing technique includes acquiring a main image of a scene and determining one or more facial regions in the main image. The facial regions are analysed to determine if any of the facial regions includes a defect. A sequence of relatively low resolution images nominally of the same scene is also acquired. One or more sets of low resolution facial regions in the sequence of low resolution images are determined and analysed for defects. Defect free facial regions of a set are combined to provide a high quality defect free facial region. At least a portion of any defective facial regions of the main image are corrected with image information from a corresponding high quality defect free facial region.

The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging ("post repair") using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

Scanning Laser Epitaxy (SLE) is a layer-by-layer additive manufacturing process that allows for the fabrication of three-dimensional objects with specified microstructure through the controlled melting and re-solidification of a metal powders placed atop a base substrate. SLE can be used to repair single crystal (SX) turbine airfoils, for example, as well as the manufacture functionally graded turbine components. The SLE process is capable of creating equiaxed, directionally solidified, and SX structures. Real-time feedback control schemes based upon an offline model can be used both to create specified defect free microstructures and to improve the repeatability of the process. Control schemes can be used based upon temperature data feedback provided at high frame rate by a thermal imaging camera as well as a melt-pool viewing video microscope. A real-time control scheme can deliver the capability of creating engine ready net shape turbine components from raw powder material.

Graphene is a single atomic layer of sp2-bonded C atoms densely packed into a two-dimensional honeycomb crystal lattice. A method of forming structurally perfect and defect-free graphene films comprising individual mono crystalline domains with in-plane lateral dimensions of up to 200 μm or more is presented. This is accomplished by controlling the temperature-dependent solubility of interstitial C of a transition metal substrate having a suitable surface structure. At elevated temperatures, C is incorporated into the bulk at higher concentrations. As the substrate is cooled, a lowering of the interstitial C solubility drives a significant amount of C atoms to the surface where graphene islands nucleate and gradually increase in size with continued cooling. Ru(0001) is selected as a model system and electron microscopy is used to observe graphene growth during cooling from elevated temperatures. With controlled cooling, large arrays of macroscopic single-crystalline graphene domains covering the entire transition metal surface are produced. As the graphene domains coalesce to a complete layer, a second graphene layer is formed, etc. By controlling the interstitial C concentration and the cooling rate, graphene layers with thickness up to 10 atomic layers or more are formed in a controlled, layer-by-layer fashion.

A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening. The second material has a thickness which is less than a critical thickness to maintain the second material in a strained state. The strained second material functions as a channel for charge carriers.

Provided are methods for forming graphene or functionalized graphene thin films. Also provided are graphene and functionalized graphene thin films formed by the methods. For example, electrophoretic deposition methods and stamping methods are used. Defect-free thin films can be formed. Patterned films can be formed. The methods can provide conformal coatings on non-planar substrates.

A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. A plurality of seed pads are then formed by self-directed touchdown by exposing the interface layer to a material comprising a semiconductor material. The plurality of seed pads, having an average width of about 1 nm to 10 nm, are interspersed within the interface layer and contact the substrate. An epitaxial layer is then formed by lateral growth of the seed pads over the interface layer.

A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

A semiconductor device includes at least one defect-free epitaxial layer. At least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on top of a surface of a first solid state material having a first thermal evaporation rate and a plurality of defects, where the surface comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects, the method including the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.

Amongst the candidates for very high efficiency solid state lights sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects. Further manufacturing requirements demand reproducible nanowire diameter, length etc to allow these nanowires to be embedded within device structures. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group III—nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. The technique also allows for unique dot-within-a-dot nanowire structures.

Methods and systems for detecting defects in patterns formed on a specimen are provided. One system includes one or more components executed by one or more computer subsystems, and the component(s) include first and second learning based models. The first learning based model generates simulated contours for the patterns based on a design for the specimen, and the simulated contours are expected contours of a defect free version of the patterns in images of the specimen generated by an imaging subsystem. The second learning based model is configured for generating actual contours for the patterns in at least one acquired image of the patterns formed on the specimen. The computer subsystem(s) are configured for comparing the actual contours to the simulated contours and detecting defects in the patterns formed on the specimen based on results of the comparing.

Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and / or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and / or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire / MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) Group III—Nitride nanostructures and uniform Group III—Nitride nanostructure arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanostructure can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed Group III—Nitride nanostructures and / or nanostructure arrays providing a uniform length of about 0.01-20 micrometers (μm) with constant cross-sectional features including an exemplary diameter of about 10 nanometers (nm)-500 micrometers (μm). Furthermore, core-shell nanostructure / MQW active structures can be formed by a core-shell growth on the non-polar sidewalls of each nanostructure and can be configured in nanoscale photoelectronic devices such as nanostructure LEDs and / or nanostructure lasers to provide tremendously-high efficiencies. Additional growth mode transitions from the pulsed to the non-pulsed growth mode and subsequent transitions from non-pulsed to pulsed growth mode are employed in order to incorporate certain group III—Nitride compounds more efficiently into the nanostructures and form devices of the designed shape, morphology and stochiometric composition. In addition, high-quality group III—Nitride substrate structures can be formed by coalescing the plurality of group III—Nitride nanostructures and / or nanostructure arrays to facilitate the fabrication of visible LEDs and lasers.

Amongst the candidates for very high efficiency electronics, solid state light sources, photovoltaics, and photoelectrochemical devices, and photobiological devices are those based upon metal-nitride nanowires. Enhanced nanowire performance typically require heterostructures, quantum dots, etc which requirement that these structures are grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. Methods of growing relatively defect free nanowires and associated structures for group IIIA-nitrides are presented without the requirement for foreign metal catalysts, overcoming the non-uniform growth of prior art techniques and allowing self-organizing quantum dot, quantum well and quantum dot-in-a-dot structures to be formed. Such metal-nitride nanowires and quantum structure embedded nanowires support a variety of devices including but not limited to very high efficiency electronics, solid state light sources, photovoltaics, and photoelectrochemical devices, and photobiological devices.

The present invention provides an oxide CMP slurry composition for use in planarizing silicon oxide-containing films via CMP during CMOS device fabrication, and a method of planarizing silicon oxide-containing films via CMP using the slurry composition. The oxide CMP slurry composition according to the invention includes: (i) proline, lysine and / or arginine; (ii) a pyrrolidone compound; and (iii) abrasive particles. Proline is presently most preferred for use in the invention. In the STI sub-process of the CMOS device fabrication process, the oxide CMP slurry composition according to the present invention acts to aggressively remove only the silicon dioxide overburden on the processed wafer that is in contact with a polishing pad, which results in the formation of a substantially planar, defect-free surface. The oxide CMP slurry composition according to the invention does not aggressively remove trench silicon dioxide thereby allowing for extended polishing beyond the end point without substantially increasing the minimum step height.

A wafer pair comprising a substantially defect-free germanium wafer and methods of making the same. The wafer pair comprises the substantially defect-free germanium wafer directly bonded to a silicon wafer. The method of making the wafer pair comprises placing the silicon wafer in a wafer-bonding chamber, placing the germanium wafer on top or on bottom of the silicon wafer, and applying a local force to either the germanium wafer or to the silicon wafer to initiate bonding of the germanium wafer to the silicon wafer. The bonding occurs under a temperature ranging from about 23° C. to about 600° C. and under a vacuum condition inside a wafer-bonding chamber.

Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and / or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and / or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire / MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

The present invention relates to reflective masks and their use for reflecting extreme ultraviolet soft x-ray photons to enable the use of extreme ultraviolet soft x-ray radiation projection lithographic methods and systems for producing integrated circuits and forming patterns with extremely small feature dimensions. The projection lithographic method includes providing an illumination sub-system for producing and directing an extreme ultraviolet soft x-ray radiation lambd from an extreme ultraviolet soft x-ray source; providing a mask sub-system illuminated by the extreme ultraviolet soft x-ray radiation lambd produced by the illumination sub-system and providing the mask sub-system includes providing a patterned reflective mask for forming a projected mask pattern when illuminated by radiation lambd. Providing the patterned reflective mask includes providing a Ti doped high purity SiO2 glass wafer with a patterned absorbing overlay overlaying the reflective multilayer coated Ti doped high purity SiO2 glass defect free wafer surface that has an Ra roughness<=0.15 nm. The method includes providing a projection sub-system and a print media subject wafer which has a radiation sensitive wafer surface wherein the projection sub-system projects the projected mask pattern from the patterned reflective mask onto the radiation sensitive wafer surface.