134 results about "Conventional memory" patented technology

A high density non-volatile memory system, card, and device is described that incorporates a synchronous interface. This is accomplished through use of an external or embedded controller and/or memory buffer to manage the high density non-volatile memory device(s) to present it as a conventional memory device having a synchronous interface that is accessible by row and column address. This allows the high density non-volatile memory to support in-place code execution and allows it to be booted from. Additionally, this incorporation eliminates the overhead of drivers and/or operating system support required to utilize and present conventional high density non-volatile memory devices and moves it internal to the memory device. This simplifies the use and design effort in the overhead and specialized interfacing of high density non-volatile memories and in particular, NAND architecture Flash memories, while reducing the production cost through use of less expensive high density non-volatile memory.

An apparatus and method are described for identifying uncommitted memory in a system RAM during an initialization process of a computer system, such as a boot procedure or power-on self test, during which memory management is uncontrolled. In various embodiments of the invention, repeating patterns that are indicative of uncommitted memory blocks are identified within a conventional memory area of the system RAM. At least some of the uncommitted memory blocks are allocated for use by an option ROM or other BIOS data and a table is created identifying these uncommitted memory blocks. After the BIOS code exits the system RAM, the table is used to restore the uncommitted memory blocks into their previous data states.

A self-descriptive microphone array includes a microphone array memory, such as, for example a ROM, EEPROM, or other conventional memory, which contains a microphone array device description. This device description includes parametric information which defines operational characteristics and configuration of the microphone array. In further embodiments, the microphone array uses any of a variety of conventional wired or wireless computer interfaces, including serial, IEEE 1394, USB, Bluetooth™, etc., to connect to a computing device. Once connected, the microphone array provides its device description to the computing device. Sound processing software residing within the computing device is then automatically configured for optimally interacting with one or more analog or digital audio signals provided by the microphone array. In another embodiment, the microphone array performs integrated self calibration for automatically updating the device description. The self calibration is performed either upon connection to the computing device, or upon regular or user-specified intervals.

An improved memory module and method of manufacture are presented. The memory module takes on the same outer dimensions as conventional memory cards. The memory module includes an integrated circuit and a conductor encased within molded resin. The conductor can be taken from a tape or a lead frame, and can include bumps or wires extending from the conductor to corresponding bonding pads on the integrated circuit. The bonded integrated circuit can thereafter be placed within a cavity formed inside a mold housing, where resin may be injected to form the memory module. The conductor can also be shaped so as to extend on multiple planes from the connection point on or near the bonding pad to an edge connector residing near one edge only of the memory module. The conductor is thereby connected to the integrated circuit and provides slide-in, releasable coupling to a receptor.

Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information.

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.

Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references. Transforming of the original computer code comprises inserting, into the original computer code, instructions to execute initialization, lookup, and cleanup operations associated with the leading memory reference and trailing memory reference in a different manner from initialization, lookup, and cleanup operations for the one or more middle memory references.

Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information.

Methods of conserving memory resources available to a computer system during execution of a system BIOS are provided. The method includes (a) executing the system BIOS; (b) loading the header, runtime code, and memory allocator code associated with the option ROM BIOS chip into the option ROM memory space; (c) passing control to the memory allocator code; (d) executing the memory allocator code to allocate conventional memory of the system RAM; (e) copying the decompressor code from the option ROM BIOS chip to the allocated conventional memory; (f) passing control to the decompressor code; (g) executing the decompressor code to decompress the compressed initialization code directly from the option ROM BIOS chip and thus loading the decompressed initialization code into the conventional memory; and (h) executing the decompressed initialization code to initialize the adapter card or controller.

An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

A circuit and method for testing an eDRAM through a test controller with direct access (DA) mode logic is provided. The circuit and method of the present invention allows the testing of eDRAMs with a conventional memory tester. The present invention provides a semiconductor device including an embedded dynamic random access memory (eDRAM) for storing data, the eDram including a plurality of memory cells, and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including built-in self-test (BIST) logic circuitry for performing tests and for interfacing to a logic tester, and direct access mode logic circuitry for interfacing the eDRAM with an external memory tester. The test controller further comprises a multiplexer for multiplexing data, commands, and addresses from the BIST logic circuitry and the direct access mode logic circuitry to the eDRAM.

In a memory system, a spare error correction bit is produced by processing data to be stored in sufficiently large chunks that the number of error correction bits required to protect each chunk are fewer than the available error correction signal lines on a memory bus and storage device. The spare bit is then used for an inversion bit in a parallel data bus inversion scheme, wherein data is selectively inverted to minimize bus switching. The transmission of data and error correction bits are spread over multiple phases, wherein parallel data bus inversion is applied to each phase. Alternatively, the transmission of data and error correction bits may be transmitted and stored in a single transaction. In either case, the spare bit is transmitted on a conventional memory bus and stored in a conventional memory module along with data and error correction bits.

There is disclosed a memory cell having a reduced active area. The memory cell may be incoporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrudes above the semiconductor substrate. The memory element, such as a memory element formed of chalcogenide material, is disposed on the side of the protrusion to reduce the active area of the memory element as compared with conventional memory elements.

A content-based information retrieval architecture is herein disclosed that can achieve correct and predictable high speed lookups while taking advantage of inexpensive conventional memory components.

A memory test device that issues a test pattern read request to a memory, captures test pattern signals placed by the memory on a data input/output bus in response to the test pattern read request, and compares the test pattern signals with their expected values. This can solve a problem involved in a conventional memory test device in that because the pin width of data pins is narrower than the bus width of the data input/output bus that connects a memory and a data bus controller, even if the memory reads test pattern signals in accordance with the width of the data input/output bus, the test pattern signals cannot be sent to the tester without being divided, and hence the tester cannot achieve the quick test of the memory.

Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem.

Miniature flash memory card with mini-SD and RS-MMC compatibility is provided. This is accomplished by a special circuit layout of the module substrate, so that the memory controller is attached on the front end of the module substrate, and two or more memory dies can be fitted in the memory block toward the back end of the module substrate, using smaller and higher density memory, whereas the conventional memory card has to use monolithic memory module. In the present design, the memory ICs are built into the memory module, but the memory can be easily replaced or added for memory expansion.

Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary method includes receiving a request from a system BIOS to locate an amount of conventional memory where the amount of conventional memory accommodates at least a decompressed version of data located in an option ROM BIOS. Then the amount of conventional memory requested by the system BIOS is determined. If the amount of conventional memory requested by the system BIOS is not available, the method continues and system BIOS data located within the conventional memory is read where the system BIOS data occupies at least the amount of conventional memory requested by the system BIOS. After the system BIOS data is read, the system BIOS data is written from the conventional memory to an extended memory, and the system BIOS data located in the conventional memory that has been written into the extended memory is deleted.

The invention discloses an embedded programmable memory based on memory IP core, which provides programmable mechanism, enables users to design the bit wide, work mode and synchronous/asynchronous output of the memory, and supports the work modes, including packet mode, single port, simple dual port and true dual port. The invention adopts an additional register to buffer conflicting data and address, utilizes the bit zone of the data bit and the read-write conflict detection and protection mechanism to realize the programmable memory; the design convenience is realized and the functional flexibility is also realized, and the functions of conventional memory are greatly extended; compared with conventional programmable memory technology, the embedded programmable memory has great improvements on speed, area, power consumption and reliability.

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array including regular memory cells and permanent memory cells and a control circuit. The regular memory cells are capable of switching between a first data storage state and a second data storage state. The permanent memory cells are fixed in a third data storage state that is read as the same logic level data as the first storage state. Data is stored in at least one of the regular memory cells and at least one of the permanent memory cells. The control circuit rewrites at least one of the regular memory cells from the second data storage state to the first data storage state at the time of data holding. The control circuit performs a reading operation after rewriting the regular memory cells from the first data storage state to the second data storage state.