Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

149results about How to "Small depth" patented technology

Mechanical lockings of floor panels and a tongue blank

ActiveUS20120017533A1Improve function and strengthFunction increaseFloorsFlooringTongue and grooveEngineering
Floor panels (1, 1′) are shown, which are provided with a mechanical locking system comprising tongue and grooves provided with protrusions and cavities which are displaceable in relation to each other.
Owner:VÄLINGE INNOVATION AB

Wiring board with built-in component and method for manufacturing the same

A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.
Owner:NGK SPARK PLUG CO LTD

Overlay error detection

An overlay target with gratings thereon is illuminated and radiation scattered by the target is imaged onto detectors. A phase difference is then detected between the outputs of the detectors to find the mis-alignment error. In another aspect, an overlay target with gratings or box-in-box structures is illuminated and radiation scattered by the target is imaged onto detectors located away from the specular reflection direction of the illumination in a dark field detection scheme. Medium numerical aperture optics may be employed for collecting the radiation from the overlay target in a bright or dark field configuration so that the system has a larger depth of focus and so that the two structures of the target at different elevations can be measured accurately at the same time. Analytical functions are constructed for the grating type targets. By finding the phase difference between the two gratings at different elevations, misalignment errors can be detected. Analytical functions are constructed as a model for box-in-box type targets where data points away from the edges of the box or bars can be used in the curve fitting. Symmetrical functions are employed to further reduce noise.
Owner:KLA TENCOR CORP

Semiconductor chip and method of manufacturing semiconductor chip

A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconductor substrate and electrically connected to the semiconductor device, a through via formed in a through hole penetrating through the semiconductor substrate and the electrode pad, and an Au bump deposited on the electrode pad and the through via such as to electrically connect between the electrode pad and the through via.
Owner:SHINKO ELECTRIC IND CO LTD

Display device having scope of accreditation in cooperation with depth of virtual object and controlling method thereof

A display device having a scope of accreditation in cooperation with a depth of a virtual object and a controlling method thereof are disclosed in this specification. The display device according to this specification outputs a three-dimensional (3D) image including virtual objects. And a scope of accreditation accrediting (or recognizing) that a virtual object has been selected is configured in the virtual object. At this point, an area of a scope of accreditation may be configured to be in cooperation with a depth of a virtual object along an increasing or decreasing direction of the depth of the virtual object, wherein the depth of the virtual object indicates a distance level between the virtual object and a user's perspective within the 3D image.
Owner:LG ELECTRONICS INC

Wafer grinding method

A wafer grinding method is disclosed, in which only a region, corresponding to a device formation region, of the back side of a wafer is ground in rough grinding conducted first, while the part surrounding the region thus ground is left unground as an annular projected part, to prevent the outer peripheral edge of the wafer from becoming knife edge-like in shape. In the subsequent finish grinding, the annular projected part is ground and, further, the whole area of the back side of the wafer is ground to be flat. Chippings of the outer peripheral edge may be generated only during the finish grinding, whereby the chippings are prevented from occurring or limited to minute ones.
Owner:DISCO CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products