93results about How to "Reduced Miller Capacitance" patented technology

Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

A semiconductor gate structure includes a shielding electrode and a switching electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

The invention discloses a trench-gate charge storage type IGBT and a manufacturing method therefor, and belongs to the technical field of semiconductor power devices. A trench-gate emitter structure connected with a P-type volume region is introduced to an N-type drift region at one side of a trench gate in a conventional CSTBT device, thereby enabling the gate-collector capacitance into gate-emitter capacitance, and improving the adverse effect of Miller capacitance. A thick dielectric layer of the trench-gate emitter structure avoids an electric field concentration effect at the bottom of atrench, and improves the breakdown voltage of a device. The depth of a gate electrode is enabled to be less than the junction depth of an N-type charge storage layer, thereby reducing the overall gatecapacitance under the condition that the connection of an IGBT is not affected, improving the switching speed of the device, reducing the switching loss of the device, and improving the compromise characteristics between a positive conduction voltage and the switching-off loss. According to the invention, the existing of the P-type volume region can reduce the extraction area of a hole, and improves the carrier concentration distribution of the whole N-type drift region. Moreover, the noise impact is reduced, and the EMI effect is avoided.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. Discontinuous gate structures are formed on the basis of the common silicon carbide MOSFET structure, two silicon carbide deep P injection regions are introduced between the two gate structure and metal or polycrystalline silicon is introduced between the two silicon carbide deep P injection regions. The metal or the polycrystalline silicon directly contacts the silicon carbide N-epitaxy so as to form the Schottky contact or the heterojunction contact having the rectification characteristic. The improvement greatly optimizes the conventional silicon carbide UMOSFET basic characteristics, realizes integration of multiple sub-rectifiers and greatly optimizes the third quadrant performance of the device. Meanwhile, the silicon carbide MOSFET device has the characteristics of low Miller capacitance, simple process and easy implementation.

The invention discloses a superjunction IGBT with a shield gate and a manufacturing method thereof. The superjunction IGBT comprises a semiconductor substrate, a cell region and a terminal protectionarea. The semiconductor substrate comprises a second conductivity type collector region, a first conductivity type field termination layer and at least one first conductivity type epitaxial layer. Thecell region comprises a plurality of cells connected in parallel with each other, which includes a plurality of cell trenches and a gate conductive polysilicon and a shield gate filled in the cell trenches, A seventh oxide layer is arranged on both sides and sidewalls of the notch of the cell trench opposite to the gate conductive polysilicon, a fifth oxide layer is arranged between the gate conductive polysilicon and the shield gate, and a fourth oxide layer is arranged on the bottom and sidewalls of the cell trench opposite to the shield gate. A P-pillar is also provided in the first conductivity type epitaxial layer, one end of the P-pillar is connected to the second conductivity type well layer, and the other end extends toward the first conductivity type field termination layer. Theinvention adopts the shielding gate structure, reduces the Miller capacitance, thereby reducing the switching loss.

The invention belongs to the technical field of power source management, and relates to an on-chip low dropout regulator with the fast transient response function. The on-chip low dropout regulator comprises an error amplifier, a power tube MP, a Miller capacitor CL, a first divider resistor and a second divider resistor, wherein the source electrode of the power tube MP is connected with input voltage VIN, and the drain electrode of the power tube MP is grounded after passing through a series structure of the first divider resistor and the second divider resistor; the negative input end of the error amplifier is connected with the reference voltage Vref, the positive input end of the error amplifier is connected with the series point of the first divider resistor and the second divider resistor, the output end is connected with the grid electrode of the power tube MP, and the Miller capacitor CL is connected between the drain electrode of the power tube MP and the ground; an error amplifier of an STCB structure is adopted, and a transient enhancing structure is inserted into the input stage of the error amplifier; a differentiator is connected between the grid electrode and the drain electrode of the power tube MP, and meanwhile a self-biasing structure is introduced into the LDO. Miller capacitance needed by loop compensation is substantially reduced while transient response speed is increased.

The invention discloses an insulated gate bipolar transistor. Compared with the prior art, polycrystalline silicon filled in a trench is separated by a dielectric layer into an upper polycrystalline silicon layer and a lower polycrystalline silicon layer, the upper polycrystalline silicon layer and the lower polycrystalline silicon layer are mutually contacted with an oxide layer at the upper part of the trench and an oxide layer at the lower part of the trench respectively, the upper polycrystalline silicon layer is connected with a gate electrode, and the lower polycrystalline silicon layer is connected with an emitting electrode; and bottom part of the upper polycrystalline silicon layer in the trench is deeper than a P-type well region of an active primitive cell. The structure disclosed by the invention reduces the Miller capacitance and the turn-on power consumption of the device.

The invention relates to a VGA stage having a novel circuit configuration for amplifying / attenuating a differential input signal which is transmitted via a transmission line (H). The VGA stage comprises an operational amplifier (OPV1, OPV2), which is connected as shunt feedback, for amplifying the input signal; a string of resistors (R01, R01') for attenuating the signal; and a control device (2) for switching the string of resistors (R01, R01').

A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). The comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.

The invention belongs to the technical field of power semiconductor devices, and relates to a RET IGBT with a self-biased PMOS and a manufacturing method thereof. According to the RET IGBT with the self-biased PMOS and the manufacturing method thereof, a N-type charge storage layer is arranged between a P-type base region and a P-type buried layer, so that the influence of the N-type charge storage layer on the breakdown voltage of the device can be shielded while the forward conduction characteristic of the device is improved; by introducing a PMOS structure, an extra path is provided for theextraction of holes, the extraction speed of current carriers is accelerated, the switching speed of the device is improved, and the turn-off loss of the device is reduced; and meanwhile, an emitterembedded type separation gate structure can meet the requirement that a table top of the device is further narrowed to improve the forward conduction characteristic of the device, metal and contact holes of the emitter of the device can be easily and irregularly made, and meanwhile, the Miller capacitance of the device can be reduced further.

The present invention achieves technical advantages as a current monitoring circuit for DC-DC switching converters, including a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). Advantageously, the comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.

A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. The invention aims at a conventional silicon carbide UMOSFET structure, and proposes a multi-sub rectifier device integration mode, and includes implementation methods of Schottky contact and Si / SiC heterojunction contact. While effectively improving the basic characteristics of the traditional carbonize UMOSFET and optimizing the long-term application reliability of the device, the invention realizes the integration of the multi-sub rectifier devices, thereby greatly optimizing the work performance of the device in the third quadrant. The implementation process of the structure is compatible with the traditional silicon carbide UMOSFET process, and has the characteristic of easy fabrication.

The present invention provides a transverse groove-type MOSFET device, belonging to the technical field of semiconductor power devices. A polycrystalline silicon region or a Schottky contact metal region is formed at the circumference side of the gate structure to allow polycrystalline silicon region or the Schottky contact metal region and the drift region to form heterojunction or Schottky contact with rectification characteristics. Because the heterojunction or Schottky contact is multiple sub devices and is lower in conduction pressure drop compared to a traditional parasitic diode, the reverse recovery characteristic of the device can be optimized, and an excellent three-quadrant on-state performance is achieved; and compared to an external antiparallel diode mode, the size of the electrical power system can be significantly reduced, the package cost is reduced, interconnection lines are reduced, and the parasitic effect of the interconnection lines is reduced so as to improve thereliability of the system. Aiming at the problem that the device gate medium electric field is too high, the optimization is design to improve the long application reliability performance of the device. Besides, the preparation method of the device is simple and controllable and easy to achieve, and promotes the popularization of the semiconductor power device in the many actual applications.

The invention discloses a heavy doping method of a source electrode and a drain electrode. According to the heavy doping method of the source electrode and the drain electrode, the ion implantation direction inclines to the direction of the source electrode and is vertical to the direction of a substrate so as to form an included angle, the heavy doping area of the source electrode and a heavy doping area of the drain electrode are of asymmetrical structures as the ion implantation direction is not vertical to the surface of the substrate, the distance between the heavy doping area of the drain electrode is far from a groove by pulling, and the area of the overlapping region between the heavy doping area of the drain electrode and a gate electrode structure is reduced, so that the parasitic overlapping capacitance between the drain electrode and the gate electrode can be reduced, further the Miller capacitance of a common-source amplifier can be reduced, and the frequency response characteristics of the common-source amplifier are improved.

The invention discloses an anti-EMI SGT device. The device comprises a substrate of a first conductive type, an epitaxial layer of the first conductive type which is positioned on the upper surface ofthe substrate of the first conductive type, a trench gate structure located in the epitaxial layer of the first conductive type, a trench source structure located above the side surface of the epitaxial layer of the first conductive type, a first dielectric layer and a heavily doped body region of the first conductive type located between the trench source structure and the epitaxial layer of thefirst conductive type, and a second dielectric layer located above the trench gate structure, wherein the trench gate structure comprises a gate trench, and a shielding gate and a polycrystalline silicon gate which are positioned in the gate trench; the trench source structure includes a source trench and a source metal located within the source trench. According to the device disclosed in the invention, the SGT source-drain capacitance Cds is increased, the switching oscillation is reduced, and therefore the voltage oscillation dv / dt failure possibility and EMI noise of the device are reduced.

The invention provides a trench insulated gate bipolar transistor device and a generating method thereof. A relatively thick gate oxide film is formed at the bottom of a trench region through a plasmafilm forming process. Due to the fact that the thickness of the gate oxide film at the bottom of a trench is increased, the consistency of the gate oxide thickness is guaranteed, the defect that a gate oxide layer at the bottom of the trench is easy to break down is eliminated, and the robustness of a gate oxide breakdown voltage is improved. Meanwhile, the area of a gate-drain capacitor is reduced, so that the Miller capacitance is reduced, the switch delay time is shortened, the switch dynamic loss of a device is reduced, and the switch characteristic of the device is improved. Meanwhile, the relatively thick gate oxide film is formed at the bottom of the trench, so that the upper surface of polycrystalline silicon subjected to back etching can be leveled and is slightly higher than thesurface of a silicon wafer of a N-type base region; and higher N+ emitter junction depth can be formed without increasing the injection energy of an N+ emitter and carrying out longer-time high-temperature trap pushing, so that the vertical overlapping area of the gate and the source is reduced, the gate-source capacitance is reduced, and the switch loss of an IGBT is reduced.

The invention discloses a bidirectional IGBT and a manufacturing method therefor, and belongs to the technical field of power semiconductor devices. According to the invention, a split electrode whichis equipotential with a surface metal and a thick dielectric layer located at a peripheral side of the split electrode are introduced to a conventional trench gate structure, and a floating P-type body region is introduced to one side of a split trench gate structure, thereby achieving the symmetric forwarding and reverse on / off characteristics of an IGBT structure under the condition that a threshold voltage and connection of an IGBT device are not affected. The adverse effect caused by the Miller effect is improved, and the drive power consumption is reduced. The current and voltage oscillation and EMI problems are avoided in a start dynamic process of the device. The short-circuit safety working area of the device is improved. The gate capacitance is reduced, the switching speed of thedevice is improved, and the switching loss of the device is reduced. The concentration of an electric field at the bottom of a trench is improved, and the breakdown voltage of the device is improved.The carrier enhancement effect of an emitter electrode is improved, the carrier concentration distribution of the whole N-type drift region is improved, and the compromise between the forwarding conduction voltage drop and switching-off loss is improved.

A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device with a MOS (Metal Oxide Semiconductor) control hole path, and belongs to the technical field of power semiconductor devices. AMOS control gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel area is introduced into a P+ floating pbody area of a traditional IGBT device, anda MOS region is equivalent to a switch under gate voltage control. When the device is conducted forwardly, the potential of the pbody area floats, so that hole storage is realized, and the saturated on-off voltage drop of the device is reduced. When the device is off and short-circuited, a hole discharge path is provided; the Miller capacitance is reduced; and the low on-off loss and more stable short circuit capability are realized.

The invention discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises a separation grating structure located in a groove; the separation grating structure comprises a first gate conductor, a second gate conductor and a third gate conductor which are separated mutually; the first part of the first gate conductor is located at the upper part of the groove and is clamped between the second gate conductor and the third gate conductor; and the second part of the first gate conductor extends to the lower part of the groove. The power semiconductor device adopts the separation grating structure to improve the response speed and reduce the switch loss.

Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

The invention provides a ring ion injection method which comprises the steps of: respectively carrying out ion injection on a source electrode and a drain electrode on a substrate, wherein an included angle of a drain electrode ion injection direction and a direction vertical to the surface of the substrate is more than that of a source electrode ion injection direction and the direction vertical to the surface of the substrate; and enabling a charge region of a drain electrode space to be compressed from a trench direction so that an overlapping area of the drain electrode and a grid electrode is compressed, thus a parasitic overlap capacitance between the drain electrode and the grid electrode of a semiconductor device is decreased, a Miller capacitance of a common-source amplifier is reduced, and the frequency response characteristic of the common-source amplifier is improved. In addition, though the charge region of the drain electrode space is compressed, a charge region of a source electrode space extends into a trench, the effective trench length of the semiconductor device is basically kept unchangeable, and other properties of the semiconductor device can be maintained.