37results about How to "Reduced board area" patented technology

A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the substrate. The semiconductor die and the solder balls are encapsulated in an overmold material on the substrate such that portions of the solder balls are exposed. A ball grid array is formed such that bumps of the ball grid array are electrically connected to the conductive traces and the integrated circuit package is singulated.

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

The invention relates to a configurable radio-frequency power amplifier and a radio-frequency transmitting front-end module with the same. The configurable radio-frequency power amplifier comprises a configurable radio-frequency power amplifier tube core (201) and a configurable output impedance matching network (202); the output end of the configurable radio-frequency power amplifier tube core (201) is connected with the configurable output impedance matching network (202); the configurable output impedance matching network (202) is provided with a plurality of impedance circuits comprising inductors and capacitors; and the configurable output impedance matching network also comprises a radio-frequency switch which controls switch-on or switch-off of each impedance circuit. The configurable radio-frequency power amplifier reduces the number of independent units of a multi-power mode radio-frequency front end and integrates two chips in a single module so that the area, occupied by the multi-power mode radio-frequency transmitting front-end module, of a circuit board of a mobile terminal is reduced, and meanwhile, the manufacturing cost of the mobile terminal is reduced.

A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe.

The invention relates to a wireless human-machine interactive device of personal computer including two parts, a display and a base. The display can be independently used separately from the base. The key features are in that: the display output module comprising at least a central processing unit (CPU) and a liquid crystal display (LCD), a main board containing a supply circuit for providing a voltage conversion for the main board and for charging a secondary battery, a backlight board, a touch screen control board, a peripheral interface board comprising all Input / Output (I / O) device interfaces and a secondary battery are mounted on a rear part of the display; an LCD control board and a supply adapter for converting a commercial supply into a direct current (DC) supply and supplying the LCD control board with power is mounted in the base; and the electrical connections between the base and the display are achieved by gilded pins (golden finger) or a multi-pin / multi-jack connector. The present invention can also be applied to a normal liquid crystal display of personal computer. While the inventive wireless human-machine interactive device or liquid crystal display ensures all the other functions, the appearance or the structure thereof is thinner, lighter, and more beautiful with a good visual and practical effect.

A vehicular programmable transceiver includes a digital radio frequency memory (DRFM) having at least one register configured to sample and hold a radio frequency input signal in response to a clock signal and to generate an output signal having a carrier frequency generated in response to the sampled and held input signal.

A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer.

In the case of mounting two serial communication interfaces such as PCI-e and USB 3.0 with standards different from each other, it is allowed to flexibly address a design change and the like, and reduce a board area. An interface device is provided with a PCI-e PHY I / F, a USB 3.0 PHY I / F with equivalent specifications of a PIPE I / F to that of the PCI-e PHY I / F, and a system controller for controlling the PCI-e PHY I / F and the USB 3.0 PHY I / F. The interface device includes a PIPE I / F bridge in which the PCI-e PHY I / F and the USB 3.0 PHY I / F are provided, and the PIPE I / F bridge selectively switches connection of the PCI-e PHY I / F or the USB 3.0 PHY I / F with the system controller.

A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

An audio tone-control circuit includes 4th-order low-pass, 4th-order band-pass, and 4th-order high-pass filter circuits. The 4th-order low-pass filter circuit has a first phase response and receives and filters an audio signal and generates a first output signal therefrom. The 4th-order band-pass filter circuit has a second phase response that is substantially equal to the first phase response and receives and filters the audio signal to generate a second output signal. The 4th-order high-pass filter circuit has a third phase response substantially equal to the first and second phase responses and receives and filters the audio signal to generate a third output signal. The audio-signal circuit also includes a combining circuit that combines the first, second and third output signals into a combined signal. Furthermore, the filter circuits may be 2nd-order filter circuits instead of 4th-order filter circuits.

A power supply circuit is disclosed which performs constant voltage control by switching frequency control and is ready for a wide range while the necessary control range of the switching frequency control is reduced. The circuit includes a primary side series resonance circuit forming a current resonance type converter, and a secondary side series resonance circuit formed from secondary windings and secondary side series resonance capacitors while a coupling type resonance circuit by electromagnetic coupling of an insulating converter transformer is formed. To obtain a single-humped characteristic from the coupling type resonance circuit, a gap of approximately 1.6 mm is formed in the core of the insulating converter transformer so as to achieve a coupling coefficient of 0.65 or less. A secondary side DC output voltage is produced from outputs of the secondary windings so as to cope with a heavy load condition.

A microcomputer capable of reducing a board area, enhancing the security, and improving the usability is provided. A microcomputer to be used in a notebook PC is disclosed, in which programs of a keyboard / power management BIOS and a system BIOS are stored in a built-in flash memory ROM. In order to set read (R) / write (W) protect to the BIOSes stored in the flash memory ROM, a read / write protect setting register is provided, and at initial setting after the release of reset, flags of R / W permission, R permission / W prohibition, W permission / R prohibition, and R / W prohibition are set to this register by a central processing unit CPU. By doing so, it becomes possible to achieve protection such as the prevention of error writing of the BIOS and the like between a host machine and the flash memory ROM via a LPC bus.

Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer.

The present invention discloses an integrated circuit (IC) driver chip for electroluminescent (EL) device, including an EL display-data-control block (DCB) and an EL display-segment-driver block (SDB), wherein said DCB stores the data for display and generates data-control-pulses for the EL segment display; and said SDB receives the data from the DCB and then drives the EL segments to display the desired information in real-time. This integrated circuit driver chip is suitable to be used to control and drive a multiple segment EL display. The applications of the IC include, but are not limited to, the display alphanumeric digits and image information. By cascading multiple IC driver chips together, it is possible to enlarge the number of display segments.

The invention provides a signal source of an S-band wave radar, and the signal source comprises a time clock distribution conversion module, a synchronous triggering module, a direct digital frequencysynthesis module 1, a direct digital frequency synthesis module 2, a phase-locked loop, a first local oscillator processing module, a radio frequency processing module and a second local oscillator processing module, wherein the time clock distribution conversion module, the synchronous triggering module, the direct digital frequency synthesis module 1, the direct digital frequency synthesis module 2, the phase-locked loop, the first local oscillator processing module, the radio frequency processing module and the second local oscillator processing module are integrated on one printed circuitboard. The output end of the time clock distribution conversion module is connected with the direct digital frequency synthesis module 1, the direct digital frequency synthesis module 2 and the phase-locked loop, and the direct digital frequency synthesis module 1 is connected with the second local oscillator processing module. The second local oscillator processing module output a second local oscillator signal, and the direct digital frequency synthesis module 2 is connected with the radio frequency processing module. The phase-locked loop is connected with the first local oscillator processing module, and the first output end of the first local oscillator processing module outputs a first local oscillator signal, and the second end is connected with a second input end of the radio frequency processing module. The signal source improves the coherence and stability of an S-band wave detection radar system.

A surface mount electrical connector for mounting to a substrate comprising a housing and a contact carried by the housing, the contact comprising a retention section held by the housing and a tine configured for mounting to a surface of the substrate wherein the tine extends from the retention section and wherein the tine lies inside an outer contour line of the housing is disclosed. A method of connecting a surface mount electrical connector to a substrate comprising the steps of providing a housing carrying a contact, the contact having a tine within a projected footprint of the housing on the substrate, attaching the housing to the substrate, inserting a jig into an opening of the housing, and bending the tine toward the substrate is disclosed.

The invention provides a small-size ultra wideband power divider, comprising a circuit board and a power division circuit arranged on the circuit board, wherein the power division circuit is provided with an input signal transmission segment connected to an input port and two output signal transmission segments connected to an output port, the input signal transmission segment and the output signal transmission segments are electrically connected by a circuit node, signal transmission path lengths of the input signal transmission segment and the output signal transmission segments are 1 / 6 lambda to 1 / 9 lambda, and a circuit matching segment used for matching line impedance and having a signal transmission path length of1 / 3 lambda to 1 / 6 lambda is further connected at the circuit node of the input signal transmission segment and the output signal transmission segments. The size of the power divider is reduced, so the power divider can be applied to more environments. The problems of line capacitance and inductance effects and impedance mismatch resulting from a shortened signal transmission branch length are overcome, and the performance of the power divider is guaranteed.

An inductor, a circuit board and a method for forming an inductor are provided. The inductor comprises: a first pad arranged on a first metal wiring layer of a circuit board; a second pad arranged on a second metal wiring layer of the circuit board; and a first hole with conducting medium filled therein, one end of the first hole being located in the first pad and the other end thereof being located in the second pad. The inductor can effectively reduce the area of the circuit occupied by the inductor.

The invention provides a device structure comprising a bottom device unit which is welded on a printed circuit board; and a top device unit which is welded on the bottom device unit. According to thedevice structure and the device layout, the layout density is increased to reduce the board occupation area of the devices in the limited space by fully utilizing the space limit of height so that thebattery capacity can be increased and the board wiring and board occupation space can be reduced, the wiring length can be effectively reduced, the impedance can be reduced and the competiveness of the product can be enhanced.

The invention discloses a miniaturized high-speed optical module capable of vertically outputting fibers, and relates to the technical field of high-speed data communication. The optical module comprises a metal plate upper shell, an optical device support, a module lower shell and an optical device assembly. The metal plate upper shell is arranged on the optical device assembly, the optical device support and the module lower shell, the optical device assembly is arranged on the optical device support and the module lower shell, and the optical device support is arranged on the module lower shell. According to the invention, the laminated structure under the PCB is arranged on the optical device on the structure and is integrally assembled on the lower shell of the module, the circuit is simplified by adopting a highly integrated chip scheme, the design of the PCB is reduced, the size of the optical module is minimized, and the size of the optical module is smaller than that of the optical module produced by the prior art; the vertical assembly form of the optical module greatly reduces the onboard area used by a user, and facilitates system integration and miniaturization design.

An upright composite common mode coil assembly includes a coil carrier and a seat. The coil carries includes two bobbins with a plurality of coils wounded thereon. The seat includes a base, a bottom portion, a top portion and a separating portion. The base has a back plate on a surface thereof, hollow portions formed at an upper position and a lower position thereof, a wire slot and an indentation are provided at either side of the back plate. The bottom portion and the top portion extend vertically from two sides of the base. A recessed portion is formed at each of the corners of the bottom portion, and a pin is inserted into each of the recessed portions. The top portion has a flat top face. The separating portion extends from another surface of the base and tapered to form a curved surface, and form two receiving slots with the top portion and the bottom portion, respectively. Each of the bobbins of the coil carrier is received in one of the receiving slots of the seat, and wires of a group of the coils are guided into some of the recessed portions through the wire slots and the indentations, and wires of another group of the coils are guided into the other recessed portions through the notches, so that the wires of the coils do not protrude out of the seat and are neatly soldered on the pins.

The invention discloses a multi-stage driving circuit. The multi-stage driving circuit comprises thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, ST1, ST2 and ST3. The source electrode and the grid electrode of the T1 are connected with an upper-stage driving signal; the drain electrode of the T1 is connected with the source electrode of the T4; the grid electrode of the T4is connected with a latter four-stage driving signal; the drain electrode of the T1 is further connected with the grid electrode of the T3 and the grid electrode of the T5; the source electrode of the T3 is connected with the drain electrode of the T2 through the first capacitor; the source electrode of the T3 is further connected with the drain electrodes of the T6, T8, T9 and T12; the drain electrode of the T5 is connected with a current-stage scanning signal, and the source electrode of the T5 is connected with a first clock signal; the grid electrode of the T5 is further connected with the drain electrode of the T5 through a second capacitor, and the source electrode of the T6 is connected with the drain electrode of the T5. According to the technical scheme, the four clock signals can be received and correspond to the four output signals at the same time, that is, the driving signals of the current stage, the later stage, the later second stage and the later third stage are output, the number of TFTs is reduced in architecture, finally, the needed circuit board area is reduced, and therefore panel frame occupation is reduced.

An upright composite common mode coil assembly includes a coil carrier and a seat. The coil carries includes two bobbins with a plurality of coils wounded thereon. The seat includes a base, a bottom portion, a top portion and a separating portion. The base has a back plate on a surface thereof, hollow portions formed at an upper position and a lower position thereof, a wire slot and an indentation are provided at either side of the back plate. The bottom portion and the top portion extend vertically from two sides of the base. A recessed portion is formed at each of the corners of the bottom portion, and a pin is inserted into each of the recessed portions. The top portion has a flat top face. The separating portion extends from another surface of the base and tapered to form a curved surface, and form two receiving slots with the top portion and the bottom portion, respectively. Each of the bobbins of the coil carrier is received in one of the receiving slots of the seat, and wires of a group of the coils are guided into some of the recessed portions through the wire slots and the indentations, and wires of another group of the coils are guided into the other recessed portions through the notches, so that the wires of the coils do not protrude out of the seat and are neatly soldered on the pins.