50results about How to "Reduce the value of parasitic capacitance" patented technology

The invention provides a transistor and a forming method of the transistor. The forming method of the transistor comprises the steps that a semiconductor substrate is provided, wherein an isolation structure is arranged in the semiconductor substrate, gate structures are arranged on the surfaces of the portions, on the two sides of the isolation structure, of the semiconductor substrate, and each gate structure comprises a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode located on the surface of the gate dielectric layer; first side walls are formed on the two sides of the gate structure, wherein the first side walls are doped silicon nitride layers; second side walls are formed on the surfaces of the first side walls, and the etching rate of each second side wall is larger than the etching rate of each first side wall; a source electrode and a drain electrode are formed in the portions, located on the two sides of the gate structures, of the semiconductor substrate; metal silicide layers are formed on the surface of the source electrode and on the surface of the drain electrode; the second side walls are eliminated; a stress layer is formed on the surface of the semiconductor substrate. By the adoption of the forming method of the transistor, the stray capacitance on the two sides of the gate structures of the transistor can be reduced, and the stress borne by the trench area of the transistor is increased.

The invention provides a COA (color filter on array) substrate, comprising a thin-film transistor array, data lines, scanning lines, pixel electrodes and common electrodes; the data lines and the scanning lines interact to define pixel units, the intersections of the data lines above the scanning lines form gaps which cross the scanning lines, two ends of each gap are connected through a jumper, and the jumpers are communicated with the data lines through second via holes. The COA substrate has the advantages that the parts of the data lines overlapping the scanning lines form the gaps, the jumps are added to the top of the substrate to connect the gaps of the data lines, the thickness of the jumpers from the film layer of the scanning lines is increased, parasitic capacitance of overlap portions is reduced, signal delay is decreased, effective charge time of the pixels is extended, and accordingly the display effect of a liquid crystal display panel is improved.

The invention discloses a capacitance type temperature compensation oil level measurement sensor which has high positioning accuracy and can achieve the effects of reducing the parasitic capacitance in the dry capacitance and compensating for the fuel oil level measuring errors caused by temperature variation. The capacitance type temperature compensation oil level measurement sensor is characterized in that an oil level measurement module comprises three coaxial metal tubes; the oil level and the oil mass are obtained depending on variation of liquid media in the tubes; the oil level signal capacitance C in proportion to the oil immersion height is output; a temperature compensation module is fixed at the bottom ends of the metal tubes via a conductor tray and a guide rod, is formed by a temperature sensing module assembled in a protective cover tube, automatically corrects errors caused by temperature difference via the guide rod in the tubes, outputs resistance R and capacitance C of the oil level measurement module, converts the resistance R and the capacitance C to current signals IC and IR forming proportional relations with the capacitance C and the resistance R and transmits the current signals IC and IR to a fuel measurement control system via a socket connected with shielded conductors.

The method includes following steps: providing a substrate, forming a trap area; a doping area is formed in the trap area, and a grid electrode is formed above the grid electrode; a source electrode area and a drain electrode area adjacent to the doping area are formed in the trap on two sides of the grid electrode.

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the steps of providing a semiconductor substrate, forming an insulating layer for covering a sacrificial layer and a plurality of first gate structures, etching the insulating layer, and forming a first opening in the surface of the sacrificial layer between the adjacent first gate structures to expose partial surface of the sacrificial layer between the adjacent first gate structures, removing the sacrificial layer, and forming a dielectric layer on the surface of the semiconductor substrate, wherein the plurality of first gate structures, and the sacrificial layer located on the surface of the semiconductor substrate and flush with the surface of the first gate structure are formed on the surface of the semiconductor substrate; the surface of the dielectric layer is higher than that of the insulating layer, and an air gap is formed in the dielectric layer between the adjacent first gate structures. According to the semiconductor device formed by the method, the parasitic capacitance between the adjacent gate structures can be reduced and the performance of a semiconductor device can be improved.

The invention discloses a contact bonding pad for reducing parasitic capacitance and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacture. The contact bonding pad comprises a bonding pad metal layer, and a full exhaust layer area formed by alternative doping of a first type semiconductor and the second type semiconductor in the adjacent areas; the full exhaust layer area is formed in the semiconductor substrate and located on the upper surface of the semiconductor substrate below the bonding pad metal layer. The full exhaust layer area exbands the distance between the bonding pad metal layer and the semiconductor substrate and reduces the parasitic capacitance value of the contact bonding pad; meanwhile, the method for manufacturing the full exhaust layer area is simple, and does not increases the manufacturing processing cost of the contact bonding pad.

In a capacitance type semiconductor dynamic quantity sensor, a sensor chip and a circuit are connected to each other through adhesive film having an elasticity of 200 MPa or less to reduce the temperature characteristic. Four bonding wires for connecting the sensor chip and the circuit chip are arranged so that each of the bonding wires is located at the center portion of each side portion of the sensor chip or at each corner portion of the sensor chip, thereby sufficiently increasing the interval between the bonding wires and thus sufficiently reducing the absolute value of the parasitic capacitance thus occurring. Therefore, even when the parasitic capacitance between the four bonding wires is varied, the variation is very small, and thus the influence on the sensor characteristic can be reduced.

A touch display device and a manufacturing method thereof are provided. The touch display device has a touch sensing area and a virtual touch area, and comprises a first and a second metal layer, filter layers, and common electrode layers. The first metal layer is arranged below an upper glass substrate, and the first metal layer includes a first touch line that is located in the touch sensing area; the second metal layer is arranged below the first metal layer, and includes a second touch line and a second virtual line, wherein the second touch line is located in the touch sensing area, the second virtual line is located in the virtual touch area, and the second touch line and the first touch line form a touch sensing element; the filter layer located in the touch sensing area covers the second touch line, and the filter layer located in the virtual touch area does not cover the second virtual line; and the common electrode layer located in the touch sensing area is not in contact with the second touch line, and the common electrode layer located in the virtual touch area is in direct contact with the second virtual line to reduce the resistance of the common electrode layer. The present invention also discloses a manufacturing method for the touch display device.

The invention discloses a sandwich type micro accelerometer with a high signal to noise ratio. The micro accelerometer comprises an upper electrode structure layer, an upper bonding contract area, a middle electrode structure layer, a lower bonding contract area and a lower electrode structure layer from top to bottom, wherein the upper electrode structure layer is provided with the upper bondingcontract area bonded with the middle electrode structure layer; the lower electrode structure layer is provided with the lower bonding contract area bonded with the middle electrode structure layer; the upper bonding contract area and the lower bonding contract area form a bonding contact layer; the upper electrode structure layer, the middle electrode structure layer and the lower electrode structure layer are fused and bonded in the upper bonding contract area and the lower bonding contract area to form a self-sealed structure; and the middle electrode structure layer comprises a moveable mass block. Stray capacitance values of the upper electrode structure layer, the lower electrode structure layer and the middle electrode structure layer on a device can be reduced to a large extent, and in case of a same electrode plate interval, the signal to noise ratio property of the sandwich type micro accelerometer can be remarkably improved.

The invention discloses a semiconductor structure and a forming method therefor, and the method comprises the steps: providing a substrate; forming metal gate structures on the substrate on the substrate, wherein each metal gate structure comprise a gate dielectric layer, a work function layer located on the gate dielectric layer, and a metal layer located on the work function layer; forming a barrier layer at the tops of the metal gate structures; forming an interlayer dielectric layer on the substrate between the metal gate structures; forming a contact hole plug passing through the interlayer dielectric layer; and carrying out the annealing treatment of the substrate after the forming of the contact hole plug. After the forming of the metal gate structures, the barrier layer is formed at the tops of the metal gate structures. The barrier layer is used for protecting the metal gate structures in the subsequent annealing treatment, and prevents the atoms liable to diffuse in the annealing treatment to diffuse to the work function layers of the metal gate structures, thereby avoiding the impact on the work function values of the work function layers, and achieving optimization of the electrical performances of a semiconductor device.

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure manufactured with the manufacturing method comprises a substrate and a grid formed on the substrate, and silicon epitaxy layers are formed at the portions, located on the substrate, of the two sides of the grid; first side walls are arranged on the side surfaces of the grid, intervals are formed between the first side walls and the silicon epitaxy layers, the surfaces of the first side walls also comprise second side walls, the second side walls cover the intervals, and air gaps areformed between the first side walls and the silicon epitaxy layers. According to the semiconductor structure and the manufacturing method thereof, the dielectric constant of the grid side walls is reduced, stray capacitance of a device is effectively reduced accordingly, and corresponding resistance-capacitance delay time is shortened.

The invention provides a domestic appliance and an apparatus for reducing disturbance voltage. The domestic appliance comprises a circuit board, a circuit board box and a metal plate; the circuit board box is made from an insulating material, and positioned between the circuit board and the metal plate, wherein the domestic appliance also comprises a metal sheet; the metal sheet is arranged between the circuit board and the circuit board box, or between the metal plate and the circuit board box; and the metal sheet, the metal plate and the circuit board are spaced at preset distances mutually, and are not electrically contacted. The invention also provides a method for reducing disturbance voltage of the domestic appliance. According to the domestic appliance and the method for reducing disturbance voltage of the domestic appliance provided by the invention, the dielectric constant and stray capacitance can be effectively lowered so as to reduce the disturbance voltage; and in addition, the domestic appliance has the advantages of simple mounting structure, convenience, and economical and practical performance.

The invention discloses an arrangement of an ESD protection circuit and a method for manufacturing the same. The ESD protection circuit comprises a substrate, a protection component and a resistor, wherein, the resistor is arranged in the region of the protection component, in part or whole area. As a result, the occupied area by the resistor is reduce and the junction parasitic capacitor generated inside the protection component, thereby reducing the manufacture cost of the ESD protection circuit and the influence of the ESD protection circuit on the whole internal circuit to the lowest.

The invention discloses a bonding welding disk lowering parasitic capacitance and a preparing method thereof, belonging to the technical field of manufacturing semiconductors. The bonding welding disk provided by the invention comprises a welding disk metal layer, a fist semiconductor doping well region, a second semiconductor doping zone and a first semiconductor high-doping zone, wherein, the fist semiconductor doping well region is formed by doping the semiconductor, the second semiconductor doping zone is formed in the fist semiconductor doping well region, and the first semiconductor high-doping zone is formed on the upper surface layer of the second semiconductor doping zone; junction capacitance formed between the first semiconductor doping well region and the second semiconductor doping zone, the junction capacitance formed between the second semiconductor doping zone and the first semiconductor high-doping zone and the junction capacitance formed between the first semiconductor doping well region and the semiconductor substrate are connected in series to lower the equivalent parasitic capacitance value of the bonding welding disk; meanwhile, the second semiconductor doping zone has simple preparing method and increases little cost of the preparing technology of the bonding welding disk.

The invention discloses a bonding welding disk lowering parasitic capacitance and a preparing method thereof, belonging to the technical field of manufacturing semiconductors. The bonding welding diskprovided by the invention comprises a welding disk metal layer, a fist semiconductor doping well region, a second semiconductor doping zone and a first semiconductor high-doping zone, wherein, the fist semiconductor doping well region is formed by doping the semiconductor, the second semiconductor doping zone is formed in the fist semiconductor doping well region, and the first semiconductor high-doping zone is formed on the upper surface layer of the second semiconductor doping zone; junction capacitance formed between the first semiconductor doping well region and the second semiconductor doping zone, the junction capacitance formed between the second semiconductor doping zone and the first semiconductor high-doping zone and the junction capacitance formed between the first semiconductor doping well region and the semiconductor substrate are connected in series to lower the equivalent parasitic capacitance value of the bonding welding disk; meanwhile, the second semiconductor dopingzone has simple preparing method and increases little cost of the preparing technology of the bonding welding disk.

A semiconductor structure and a fabricating method of the same are provided. The semiconductor structure includes a substate; a first low dielectric constant dielectric layer covering the substate and having a first area and a second area; a plurality of conductive member in the low dielectric constant dielectric layer; an upper lid layer positioned on at least a part of the conductive member; and a dielectric upper lid layer covering the second area of the first low dielectric constant dielectric layer and not covering the first area, wherein the conductive member positioned in the second area has a wider space than the conductive member positioned in the first area. The dielectric upper lid layer preferably has an invariable compressing stress.

The invention relates to a layout structure for shift buffer circuits, which comprises a first shift buffer and a second shift buffer arranged adjacent to the first shift buffer. A first signal and a second signal are received by the first shift buffer and the second shift buffer. The second signal and the first signal are reversed phases to each other. In addition, the first shift buffer and the second shift buffer share the signal line so as to receive the first signal. The shared signal line extends between the first shift buffer and the second shift buffer.

An array substrate is disclosed. A gate line group, common electrode line and two adjacent data lines together defining a pixel unit which has: a thin film transistor; a first and second pixel electrode disposed between the gate line group and the common electrode line; a sharing capacitor disposed between the gate line group and the pixel electrodes. The pixel units are arranged in a plurality of rows along the extending direction of data line, two adjacent pixel units are arranged sequentially in opposite direction. By using each of the sharing capacitors of the adjacent pixel units, the light leakage regions will be away from the openings of the pixel electrodes, therefore the movable mura can be eliminated without increasing the width of the black matrix and the aperture ratio loss can be solved.

The invention discloses a non-fully-convex dioctahedral transformer Balun which comprises an encircled pattern formed by encircling a primary winding and a secondary winding at a certain interval, wherein the encircled pattern has a dioctahedral structure; and sixteen angles include eight convex outer angles and eight concave inner angles which are arranged close to one another. The transformer Balun has a novel structure, small chip area, high resonant frequency and high primary and secondary inductance. High resonant frequency and high primary and secondary inductance can be provided on a system on a chip, the transformer Balun can be manufactured under the processing conditions of a BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor Transistor) and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor), high quality factor, high resonant frequency and high primary and secondary inductance are realized, and only small ship area is consumed.

An array substrate is disclosed. A gate line group, common electrode line and two adjacent data lines together defining a pixel unit which has: a thin film transistor; a first and second pixel electrode disposed between the gate line group and the common electrode line; a sharing capacitor disposed between the gate line group and the pixel electrodes. The pixel units are arranged in a plurality of rows along the extending direction of data line, two adjacent pixel units are arranged sequentially in opposite direction. By using each of the sharing capacitors of the adjacent pixel units, the light leakage regions will be away from the openings of the pixel electrodes, therefore the movable mura can be eliminated without increasing the width of the black matrix and the aperture ratio loss can be solved.