Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided. The forming method involves a first dielectric layer, a metallide and a second dielectric layer. The first dielectric layer is located on a substrate, covers the side walls of a gate, and has first grooves. The first grooves extend from the first dielectric layer of device regions to the first dielectric layer of isolation regions, and the top and side wall surfaces of source-drain doping layers are exposed at the bottoms of the first grooves. The metallide is located on the surfaces of the source-drain doping layers exposedat the bottoms of the first grooves. The second dielectric layer is located in the grooves of the isolation regions, and exposes the metallide on the top surfaces of the source-drain doping layers. The second dielectric layer can reduce the projection pattern area of the electrical connection structure of the isolation regions on the side wall surface of the gate, so as to reduce the value of parasitic capacitance formed by the electrical connection structure, the gate and the first dielectric layer between the electrical connection structure and the gate and improve the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous advancement of semiconductor technology, the feature size of semiconductor devices is gradually reduced. The reduction of critical dimensions means that more transistors can be arranged on the chip, and at the same time, higher requirements are placed on the semiconductor process. [0003] Because metal has good electrical conductivity, in semiconductor technology, the electrical connection between the source and drain doped regions and external circuits is usually realized through metal plugs. However, due to the large difference in the Fermi level between the metal and the semiconductor, the potential barrier between the metal plug and the source-drain doped region is relatively high, resulting in a relatively low contact resistance between the metal pl...

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Problems solved by technology

[0004] However, the semiconductor structure formed in the prior art still has the problem of large contact resistance or large parasitic capacitance between the metal silicide and the source-drain doped region

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