Semiconductor transistor structure and preparation method thereof

Abstract

The present invention provides a semiconductor transistor structure and a preparation method thereof. The structure comprises: a semiconductor substrate; a grid module located on the semiconductor substrate, wherein the grid module comprises a grid dielectric layer and a grid conductive layer located on the grid dielectric layer; a side wall isolation structure located at the side wall of the gridmodule, wherein the side wall of the grid module comprises a first isolation layer, an air insulation layer and a second isolation layer arranged in order from inside to outside; and bolt conductivelayers located at two sides of the grid module, wherein the side wall isolation structure is configured to separate the bolt conductive layers from the grid module. The semiconductor transistor structure and the preparation method thereof can effectively reduce the stray capacitance value so as to improve the resistance-capacitance delay increasing speed and reduce the switching energy.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a semiconductor transistor structure and a preparation method thereof. Background technique [0002] With the rapid development of integrated circuit technology, the density of devices in integrated circuits is getting higher and higher, and the feature size of semiconductor devices is continuously reduced, especially the shortening of effective gate length and short-channel effect (Short-channel effect). The leakage problem caused by channel effects, the hot carrier effect (Hot carrier effect) and other problems pose challenges to the reliability of the device. [0003] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure is widely used in the process layout of semiconductor integrated circuits (IC). In the structure of MOSFET, it is necessary to form a side wall insulating layer on the side wall to isolate the plug conductive layer from the gate c...

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Problems solved by technology

[0003] Metal-oxide-semiconductor field-effect transistor (MOSFET) structure is widely used in the process layout of semiconductor integrated circuits (IC). In the MOSFET structure, a sidewall insulating layer must be formed on the sidewall to isolate the plug conductive layer from the gate conductive layer. layer, so as to avoid the short circuit of the two conductor layers from causing the failure of the device (Device), but it also generates parasitic capacitance

As the process of DRAM (Dynamic Random Access Memory) continues to shrink to the nanometer level, it is a big challenge to improve the parasitic capacitance between the gate and the contact conductor under the condition of greatly shrinking the device

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