31results about How to "Reduce control logic" patented technology

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption / drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

The invention provides a maximum-power-point global scanning method, an inverter and a photovoltaic system. The maximum-power-point global scanning method includes: firstly, judging whether global scanning is needed or not; secondly, when global scanning is needed, subjecting busbar voltage of the inverter in the photovoltaic system to judgment, maximum-power-point scanning and processing; thirdly, processing operating states of DC (direct current) / DC converters; fourthly, subjecting multi-channel PV input to maximum-power-point global scanning so as to find a maximum power point of each PV array; finally, after maximum-power-point global scanning is terminated, subjecting the multi-channel PV input of the inverter to normal MPPT (maximum power point tracking) scanning. By the maximum-power-point global scanning method, the problem that global scanning of multi-channel PV input of an inverter lacks in the prior art is solved, generating capacity is increased and system control logic is reduced.

The present application provides a lubricating oil valve controlled by external air, which includes: a valve housing with a housing chamber, a lubricating oil inlet at its side, and a lubricating oil outlet at its lower end, the lubricating oil outlet communicates with the lubricating oil inlet, wherein The upper part has a stepped part, and an outer culvert air inlet connected to the receiving chamber is arranged on the stepped part; a T-shaped spool is arranged in the receiving chamber, and the T-shaped spool can adjust the lubricating oil between the lubricating oil inlet and the lubricating oil outlet. Flow rate, the outer side of which is provided with a sealing groove, the sealing groove is provided with an expansion ring, and the T-shaped valve core is provided with a spring outer guide sleeve, wherein a sealing ring is provided between the end of the T-shaped valve core and the valve housing; The blocking cover fixedly connected with the valve housing is provided with a through hole communicating with the atmospheric environment, and the blocking cover is provided with a spring inner guide; the spring is arranged between the T-shaped valve core and the blocking cover. By constructing the steady-state control model of the oil valve in the low state and the steady-state control model in the high state, the opening and closing of the oil valve under the control of the trapped air is realized.

The invention relates to the technical field of designing a hydrogen power generation device, and discloses a continuous hydrogen generation power generation device, including a hydrogen generation system and a fuel cell power supply system. The hydrogen generation system includes a plurality of independent solid hydrogen storage devices and water supply units And the gas delivery unit, the water supply unit can only inject reaction water into one of the solid hydrogen storage devices at the same time and when the volume of reaction water in the solid hydrogen storage device is greater than the threshold value or the temperature in the solid hydrogen storage device is greater than the threshold value The reaction water is discharged. When the hydrogen flow rate in the solid hydrogen storage device is less than the power supply required by the fuel cell power supply system, the water supply unit pumps out the reaction water in the solid hydrogen storage device, and after the reaction of the raw materials in the solid hydrogen storage device is completed, The water supply unit supplies water to the next solid hydrogen storage device according to the power generation needs of the fuel cell power supply system. The present invention can continuously produce hydrogen to achieve the purpose of power generation.

The invention relates to the field of photoelectric communication, and discloses a data transmission method and system for a digital video optical transceiver system. Adjust the coding redundancy according to the bit error rate, dynamically determine whether to adopt the forward error correction coding method and the forward error correction decoding method of the coding redundancy, so as to realize the adaptive detection of the forward error correction coding / decoding technology Error and error correction. In the present invention, the following steps are included: receiving video data and information representing the coding redundancy of the video data through an optical fiber; according to the information representing the coding redundancy, selecting a corresponding forward error correction decoding method to decode the video data; calculating The bit error rate of the decoded video data; according to the bit error rate, adjust the coding redundancy; according to the adjusted coding redundancy, select the corresponding forward error correction coding method to encode the video data to be sent; send the video data through the optical fiber and information representing coding redundancy.

The invention discloses a method and device for transmitting a branch target predicted address in a pipeline. The method includes initializing a read-write pointer of a predicted address queue and a queue free item number register; in the instruction fetch stage, according to the branch direction prediction result, the The target predicted address of the branch that predicts the jump is written into the predicted address queue, and the queue write pointer and the queue free item number register are updated; the branch direction prediction result is passed through the pipeline stage by stage; when the branch instruction of the predicted jump is dispatched in the dispatch stage, Use the read pointer to read the predicted address queue to obtain the target predicted address of the branch, and update the read pointer and the number of free items in the queue register; when the clearing operation of the pipeline occurs, reset the read and write pointer of the predicted address queue and the number of free items in the queue register. is the initial value. The present invention has the advantages of simple logic implementation and small area overhead.

The invention provides a floating point processing unit integration circuit of an of RISC processor. The circuit comprises seven stages of fixed point pipelines, six stages of floating point pipelines and an and gate. An integration method includes the steps of controlling and managing processor pipeline stall and executing and controlling all the stages of the floating point pipelines. The floating point pipelines are correspondingly set, a storage access module access control logic and an exception handling module exception handling logic in the fixed point pipelines are used together, in this way, the floating point integration structure is made clear, less modification is conducted on the original fixed point pipeline design logic while the original fixed point processor logic is fully utilized, the control logic of the floating point pipes is reduced, and power consumption is lowered; the integration method has the universality, cooperative work of the fixed point pipelines and the floating point pipelines is achieved, fixed point command execution and floating point command execution are jointly achieved, reading of two source operands and writing-in of one operation result are completed within one clock period without other special waiting periods, and efficiency is high.

The present invention relates to the field of intelligent attendance technology, specifically an intelligent access control-based attendance system and method. The system includes an attendance terminal and a cloud platform. The attendance terminal is used to obtain the uploaded results of the attendance information when uploading the attendance information; When the upload result of the attendance information is upload failure, the attendance terminal is also used to record the attendance information, and when the upload result of the attendance information is uploaded successfully, the attendance terminal is also used to upload the recorded attendance information. With this solution, when the network connection fails, the attendance information can be stored in the attendance terminal, and when the network connection is restored, the stored attendance information can be uploaded to the cloud platform. By continuing to upload the attendance information, the attendance records of all employees can be completely uploaded. To the cloud platform; at the same time, it can reduce the relevant control logic of the attendance terminal for networking requests, reduce development costs and development time; compared with continuously sending networking requests, it can also reduce the power consumption of the attendance terminal.

The invention discloses a bitmap computing method, device, equipment and storage medium. The method includes: acquiring an operation chain for performing computing operations on multiple target bitmaps; converting the operation chain into an operation of a runnable tree structure tree; run the operation tree to perform bitmap calculation. The solution described in the embodiment of the present invention automatically generates a dependency relationship tree between various operations according to the operation chain of multiple target bitmaps, so as to simplify the logic of complex bitmap operations and save the user's control logic for intermediate results.

The invention relates to the communication technology and discloses an RS (reed Solomon) decoding method and device thereof in the communication system. By serial decomposition calculation of common parallel iBM algorithm, hardware resource required for solving key equations is greatly reduced and path delay is reduced under the condition of no influence on continuous decoding. Also, by combining and optimizing Chien search and Forney algorithm process, that is, odd-even terms in error position polynomial terminals and error value polynomial terms are split, and control logic and repeated calculation is reduced. Therefore, consumption of the hardware resource is only 1 / 2 to 1 / 3 of that of the common iBM algorithm, the maximum clock frequency and effective data bandwidth are improved by about 30%, high-speed channel error technology can be applied on a low-density chip, and cost is reduced.

The invention provides a graphics primitive preprocessing method, a graphics primitive processing method, a graphic processing method, a graphics primitive preprocessor, a graphics primitive processor and a graphic processing device. The graphics primitive preprocessing method comprises the following steps: simulating the actual output process of a graphics primitive, acquiring index values of all peaks of the graphics primitive during cache, acquiring a peak index sequence table through reordering, and giving the amount of peaks of the graphics primitive to be substituted. The graphics primitive processing method comprises the step of outputting the graphics primitive and substituting the peak data during cache. The graphic processing method comprises the step of processing all graphics primitives in sequence by the graphics primitive processing method in the order of graphics primitive strings. The graphics primitive preprocessor comprises a simulating unit, an index value unit, a reordering unit and a peak amount unit. The graphics primitive processor comprises an output unit and a substituting unit. The graphic processing device comprises a reception unit, a graphics primitive preprocessor and a graphics primitive processor. According to the invention, a traditional cache mark is not required, so that the area of a chip is saved, and the design complexity and power consumption of the chip are reduced as well.