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System and method for carrying out configuration on memories

A memory and storage block technology, applied in the direction of memory address/allocation/relocation, input/output to record carrier, etc., can solve the problems of complex hardware structure and high configuration cost, and achieve less control logic, power saving, and flexibility high effect

Inactive Publication Date: 2012-07-04
北京国睿中数科技股份有限公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0005] However, in the prior art, the research on dynamically configurable memory mostly focuses on the design of the basic unit structure of SRAM, the hardware structure of this kind of design is complicated and the configuration cost is high

Method used

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  • System and method for carrying out configuration on memories
  • System and method for carrying out configuration on memories
  • System and method for carrying out configuration on memories

Examples

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example 1

[0080] Example 1: In Figure 2a , assuming that the total size of the memory 110 is 256KB, and the ratio of Cache to SRAM is 1:3, then the size of Cache is 64KB. Assuming that the Cache is a four-way set associative, the size of each way is 16KB. If the size of each line of the Cache is 32B, each way of the Cache has 512 lines. Therefore, the size of the SRAM is 192KB, that is, 256KB−64KB=192KB.

[0081] In this case, the address of Cache is divided into:

[0082] 31 .. 14 13 .. 5 4 .. 2 1 .. 0 logo group address inline word address byte address

[0083] And, the address of SRAM is divided into:

[0084] 17 .. 16 15 .. 14 13 .. 5 4 .. 2 1 .. 0 row block address block address row address inline word address byte address

[0085] In this case, the row block address of the SRAM, that is, the 17:16 bits of the SRAM address, is only valid at 00, 01, and 10, and is invalid at 11, because the SRAM is not available at this ti...

example 2

[0086] Example 2: In Figure 2b In the example, assuming that the total size of the memory 110 is 256KB, and the ratio of the Cache to the SRAM is 1:1, then the size of the Cache is 128KB. Assuming that the Cache is a four-way set associative, the size of each way is 32KB. If the size of each line of the Cache is 32B, then each way of the Cache has 1024 lines. The Cache may consist of two 16KB storage blocks. Therefore, the size of the SRAM is 128KB, that is, 256KB−128KB=128KB.

[0087] In this case, the address of Cache is divided into:

[0088] 31 .. 15 14 .. 5 4 .. 2 1 .. 0 logo Group No inline word offset byte offset

[0089] Among them, the 14th bit is used to select memory blocks of different rows. And, the address of SRAM is divided into:

[0090] 16 15 .. 14 13 .. 5 4 .. 2 1 .. 0 row block address block address row address inline word address byte address

[0091] When the memory 110 is configured as an SR...

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Abstract

The invention discloses a system and a method for carrying out configuration on memories. The system comprises a memory, a configuration register, an arbiter, a Cache (cache memory) controller and an SRAM (static random access memory) controller, wherein the configuration register is used for storing multiple configuration information of a Cache and an SRAM; the arbiter is coupled with the configuration register and receives a memory access request from the outside of an memory; and the Cache controller and the SRAM controller are parallelly arranged between the arbiter and the memory. The arbiter determines how to configure the memory into a Cache and an SRAM according to the memory access request and the multiple configuration information (stored in the configuration register) of the Cache and the SRAM, and sends obtained determining results to the Cache controller and the SRAM controller. The Cache controller and the SRAM controller respectively initiate an operation on the memory according to the determining results of the arbiter. By using the system and method disclosed by the invention, a memory can be dynamically configured into a Cache and an SRAM, and the proportions of the two can be adjusted, therefore, the memory is suitable for different applications, and high in flexibility.

Description

technical field [0001] The invention relates to the field of digital signal processor design, in particular to a system and method for configuring memory. Background technique [0002] A digital signal processor (DSP) is a microprocessor suitable for digital signal processing operations, mainly used to realize various digital signal processing algorithms in real time and quickly. Digital signal processors are widely used in computers, communications, and consumer electronics. With the development of the field of digital signal processing, the ever-increasing application requirements and applications put forward higher requirements for digital signal processors, and digital signal processors must adapt to the needs of different occasions. [0003] Static random access memory (SRAM) has the advantages of fast access speed, continuous read and write, direct address access, etc., and is widely used in digital signal processing and other fields. Cache memory (Cache, referred to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F3/06
Inventor 冯睿鑫
Owner 北京国睿中数科技股份有限公司
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