Floating point processing unit integration circuit and method of RISC processor

Abstract

The invention provides a floating point processing unit integration circuit of an of RISC processor. The circuit comprises seven stages of fixed point pipelines, six stages of floating point pipelines and an and gate. An integration method includes the steps of controlling and managing processor pipeline stall and executing and controlling all the stages of the floating point pipelines. The floating point pipelines are correspondingly set, a storage access module access control logic and an exception handling module exception handling logic in the fixed point pipelines are used together, in this way, the floating point integration structure is made clear, less modification is conducted on the original fixed point pipeline design logic while the original fixed point processor logic is fully utilized, the control logic of the floating point pipes is reduced, and power consumption is lowered; the integration method has the universality, cooperative work of the fixed point pipelines and the floating point pipelines is achieved, fixed point command execution and floating point command execution are jointly achieved, reading of two source operands and writing-in of one operation result are completed within one clock period without other special waiting periods, and efficiency is high.

Description

Technical field [0001] The invention relates to the field of embedded processors, in particular to a floating point processing unit integrated circuit and method of a RISC processor. Background technique [0002] As engineering applications have higher requirements for processor calculation accuracy, the processor is required to support single, double, or even quad precision floating-point instruction operations, and most of the floating-point instruction operations are completed in independent floating-point execution units. Therefore, it is necessary to study how to integrate the floating-point processing unit according to the floating-point execution unit. [0003] At present, there are many technologies to improve the floating-point pipeline, such as the patent "full-pipeline 128-bit precision floating-point accumulator based on full expansion" (CN 201010180381.8), "a five-stage pipeline structure of floating-point multiply-add fusion unit" (ZL200710099408) .9), but they are n...

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Problems solved by technology

The patent "Integrated System and Method of Extended Double-precision 80-bit Floating-point Processing Unit in Processor" (Application Publication No.: CN104156195A) provides a 5-stage double-precision extended double-precision 80-bit floating-point processing unit In the integrated method of the processor, but the integrated method needs to wait for the four-stage pipeline of the floating-point instruction to be executed before pre-decoding the fixed-point instruction, which directly reduces the execution performance of the instruction. In addition, a multi-precision floating-point The execution state of the instruction changes to the execution state of multiple single-cycle instructions. It is also necessary to control and manage the instruction fetch and pre-decoding module to ensure that no new instruction is read and decoded during the execution cycle of the floating-point instruction. The design logic of the processor pipeline has many modifications, and the integration method is not universal

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