38results about How to "High-speed writing" patented technology

A magnetoresistance effect element includes: a first ferromagnetic layer having invariable magnetization perpendicular to a film plane; a second ferromagnetic layer having variable magnetization perpendicular to the film plane; a first nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer on an opposite side of the second ferromagnetic layer from the first nonmagnetic layer, and having variable magnetization parallel to the film plane; and a second nonmagnetic layer interposed between the second and third ferromagnetic layers. Spin-polarized electrons are injected into the second ferromagnetic layer by flowing a current in the direction perpendicular to the film planes between the first and third ferromagnetic layers, precession movement is induced in the magnetization of the third ferromagnetic layer by injecting the spin-polarized electrons, and a microwave magnetic field of a frequency corresponding to the precession movement is applied to the second ferromagnetic layer.

There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.

A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.

Semiconductor lasers for respective wavelengths have window regions with different lengths so as to obtain optimum FFPs for emitted light of the respective wavelengths, and thus dependence on optical output can be equal between the wavelengths, facilitating the design of an optical system.