31results about How to "Good sidewall morphology" patented technology

The invention provides a method for forming self-alignment duplex pattern. The method comprises the following steps: providing a material layer to be etched, forming a sacrificial photoresist layer on the material layer to be etched, curing the sacrificial photoresist layer, forming a first mask pattern on the side wall surface of the sacrificial photoresist layer, and removing the sacrificial photoresist layer. As the sacrificial photoresist layer is cured, the hardness of the sacrificial photoresist layer is increased, and during the process of forming the first mask pattern, the sacrificial photoresist layer does not deform under the stress generated by the first mask material layer, so that the side wall of the sacrificial photoresist layer is still perpendicular to the surface of the material layer to be etched, and finally, the side wall of the etched pattern which is formed by etching the material layer to be etched has a better profile.

A formation method of a semiconductor device includes providing a substrate having a to-be-etched layer including a graph dense zone and a graph sparse zone; forming a first mask layer having sparse images on the surface of the graph sparse zone of the to-be-etched layer; forming a photo-etching layer covering the surface of the to-be-etched layer and the surface of the first mask layer; performing exposure development on the photo-etching layer and forming a second mask layer having dense images on the image dense zone of the to-be-etched layer and the surface of the first mask layer; etching the graph dense zone of to-be-etched layer by taking the second mask layer as a mask and etching the graph sparse zone of the to-be-etched layer by taking the second mask layer and the first mask layer as the mask until the surface of the substrate is exposed. By adopting the invention, problems caused by load effect during an etching process can be solved, so that the etching layer formed after the etching process of the graph sparse zone has a good appearance.

The invention provides a method for manufacturing a metal nanowire, a semiconductor device and a method for manufacturing the same. After covering a patterned core layer and a surface of a semiconductor substrate with a metal layer, first form a side wall on the side wall of the metal layer, and then Under the protection of the sidewall, the metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the sidewall is removed, thereby forming an L-shaped structure sandwiched between the patterned core layer and the sidewall. The metal nanowires have better sidewall morphology and higher thickness uniformity, thereby improving device performance and product yield.

The invention discloses a forming method of a resistance-type random access memory. The forming method comprises the following steps: using a hard mask layer with an opening as a mask, etching a top electrode layer with a first dry method etching technology until the surface of a dielectric material layer is exposed, wherein etching gas of the first dry method etching technology is CH4; continuously using the hard mask layer with the opening as the mask, etching the dielectric material layer with a second dry method etching technology until the surface of a bottom electrode layer is exposed, wherein etching gas of the second dry method etching technology is H2. According to the forming method, the etching technologies are prevented from causing etching pollution on the top electrode layer and the dielectric material layer, so that the side wall of the top electrode layer and the side wall of the dielectric material layer after etching are clean, and then the electrical property of the formed resistance-type random access memory is improved.

The invention provides a formation method of a semiconductor structure. The method includes the following steps that: a substrate is provided, a plurality of active regions are arranged in the substrate, and isolation structures are arranged between adjacent active regions, the substrate surfaces of a part of the active regions are provided with gate structures, two sides of each gate structure are respectively provided with a source region and a drain region; a first dielectric layer is formed on the surfaces of the active regions, the isolation structures and the gate structures; the first dielectric layer on the isolation structures is removed, initial through holes are formed in the first dielectric layer; a protective layer is formed on the surfaces of the side walls of the initial through holes; after the first dielectric layer at the bottoms of the initial through holes is removed, first through holes are formed in the first dielectric layer; a second dielectric layer is formed in the first through holes; after the first dielectric layer is removed, a second through hole and a source line trench are formed at two sides of each gate structure respectively; and drain conductive structures are formed in the second through holes, and source line conductive structures are formed in the source line trenches. The semiconductor structure formed by adopting the method has a beautiful appearance and stable performance.

The invention provides a super junction and its manufacturing method, and a method for manufacturing a deep trench of a super junction. The method of manufacturing a deep trench of a super junction is formed on a substrate or formed on a substrate by a polymer gas pair. The mask layer on the epitaxial layer is etched to form a hard mask, and the substrate or the epitaxial layer formed on the substrate is etched step by step through the hard mask with stepwise increasing gas pressure, so that A deep trench is formed on the substrate or an epitaxial layer formed on the substrate. The invention can form deep grooves with better feature size uniformity, better depth uniformity and better angle uniformity.

The invention provides a formation method of a semiconductor structure. The formation method comprises the steps that a first mask layer crossing a dielectric layer between the adjacent gate structures is formed on the surface of the dielectric layer; a side wall layer is formed on the surface of the sidewall of the first mask layer on the surface of the dielectric layer between the adjacent gate structures; a second mask layer having an opening is formed on the surface of the first mask layer and the surface of the dielectric layer, and the opening crosses the first mask layer and the side wall layer; the dielectric layer exposed out of the side wall layer and the first mask layer is etched along the opening with the second mask layer acting as the mask until the surface of a substrate is exposed, and discrete contact holes are formed in the dielectric layer between the adjacent gate structures; the second mask layer and the first mask layer are removed; and conductive plugs fully filling in the contact holes are formed. The sidewall position accuracy and the shape accuracy of the formed contact holes are improved so as to enhance the electrical performance and the yield rate of the formed semiconductor structure.

A self-aligned double patterning formation method comprises the steps of providing a material layer to be etched, forming a sacrificial photoresist layer on the material layer to be etched, forming a polymer layer on the surfaces of the top and the side walls of the sacrificial photoresist layer, forming a first mask material layer on the surface of the polymer layer, and back-etching the first mask material layer to enable the first mask material layer on the two sides of the sacrificial photoresist layer to form a first mask pattern. As the polymer layer is formed on the surfaces of the top and the side walls of the sacrificial photoresist layer, and the hardness of the polymer layer is far higher than that of the sacrificial photoresist layer, the shape of the sacrificial photoresist layer does not deform due to stress generated by the first mask material layer. Moreover, the rotation angle of the polymer layer formed by the use of a deposition process and an etching process is a right angle, which enables the sidewall morphology of the final etched pattern to be good.