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Formation method of semiconductor structure

A semiconductor and dielectric layer technology, applied in the field of semiconductor structure formation, can solve the problem that the electrical properties of semiconductor structures need to be improved, and achieve the effects of improving electrical properties, reducing time, and avoiding secondary pollution

Active Publication Date: 2019-03-29
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the electrical properties of semiconductor structures formed by existing technologies still need to be improved

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0033] It can be seen from the background art that the electrical performance of the semiconductor structure formed in the prior art needs to be improved. For example, the breakdown voltage (VBD: Breakdown Voltage) of the semiconductor structure is low, and there is a time-dependent dielectric breakdown (TDDB: TimeDependent Dielectric Breakdown) problem.

[0034] refer to figure 1 , the formation of the semiconductor structure includes the following steps: providing a substrate 100 in which an underlying metal layer 101 is formed; forming a dielectric layer 102 on the surface of the substrate 100; etching the dielectric layer 102 to form a thickness of the opening 103 ; forming a conductive layer filling the opening 103 , and the conductive layer is electrically connected to the underlying metal layer 101 .

[0035] After research, it is found that the reasons for the low breakdown voltage of the semiconductor structure and the significant time-dependent dielectric breakdown p...

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Abstract

A forming method of a semiconductor structure comprises: providing a substrate, wherein a dielectric layer is formed at the surface of the substrate; etching to remove the dielectric layer of first thickness by means of first etching process, and forming a pre-opening in the dielectric layer; depositing a silicon layer at the bottom and sidewall surface of the pre-opening by means of depositing process; etching to remove the silicon layer at the bottom surface of the pre-opening by means of second etching process, and etching to remove the dielectric layer of second thickness below the pre-opening; repeating the depositing process and the second etching process until an opening running through the dielectric layer is formed, and exposing the bottom of the opening to the surface of the substrate; forming a conductive layer filling the opening. The shape of the sidewall of the formed opening is improved, breakthrough voltage of the semiconductor structure that is formed is improved, and the breakthrough problem of time related media is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous advancement of VLSI process technology, the feature size of semiconductor devices has been continuously reduced, and the chip area has continued to increase. The delay time of the interconnect structure can be compared with the device gate delay time. People are faced with the problem of how to overcome the significant increase in RC (R refers to resistance, C refers to capacitance) delay due to the rapid increase in connection length. In particular, due to the increasing influence of the capacitance between metal wirings, the performance of the device is greatly reduced, which has become a key restrictive factor for the further development of the semiconductor industry. In order to reduce the RC delay caused by interconnection, various measures have been adopted...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/311H01L21/3213
CPCH01L21/311H01L21/3213H01L21/76802
Inventor 张海洋张城龙周俊卿
Owner SEMICON MFG INT (SHANGHAI) CORP
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