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Formation method of three-dimensional memory step structure

A memory and step technology, which is applied in the manufacturing of semiconductor devices, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of non-smoothness, high consumption of photoresist layer, and damage to the step layer.

Active Publication Date: 2020-12-11
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Because there are many step layers, the photoresist layer will be etched vertically while etching the photoresist layer horizontally, and the photoresist layer will be consumed, so it is necessary to form a thicker photoresist layer, otherwise it will There is a problem that the photoresist layer is consumed too much and the step layer is damaged
Since the photoresist is a relatively soft material, it is easy to produce rough sidewalls during lateral etching, which will cause the formation of photoresist mask patterns when they are transferred down to silicon nitride and silicon oxide films. The roughness of the sidewall of the step is high, which affects the accuracy of the step size and the subsequent control gate filling process, etc.

Method used

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  • Formation method of three-dimensional memory step structure
  • Formation method of three-dimensional memory step structure
  • Formation method of three-dimensional memory step structure

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Embodiment Construction

[0023] The specific implementation of the method for forming the three-dimensional memory step structure provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] Please refer to figure 1 , providing a substrate 100 on which a stack structure 110 is formed, and the stack structure 110 includes a core region I and a stepped region II surrounding the core region I.

[0025] The substrate 100 can be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, etc.; according to the actual requirements of the device, a suitable semiconductor material can be selected as the substrate 100, which is not limited here. In this specific implementation manner, the substrate 100 is a single crystal silicon wafer.

[0026] The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other along a direction perpendicular to the surface of the substrate 100 . In a...

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Abstract

The present invention relates to a method for forming a stepped structure of a three-dimensional memory, comprising: providing a substrate on which a stacked structure is formed, the stacked structure including a stepped area; forming a mask layer on the surface of the stepped area, and The mask layer includes at least a first sub-mask layer whose hardness is greater than that of the organic polymer layer; using the mask layer as a mask, step etching is performed on the step region of the stacked structure to form a step structure. The above method can improve the sidewall morphology of the formed step structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a step region of a three-dimensional memory. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] In the existing 3D NAND, it is necessary to form a stepped area on the periphery of the stacked structure, so that the contact hole can be etched later to connect the control gate. In the forming process of the steps, the photoresist is used as a mask layer, and afte...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L27/11548H01L27/11556H01L27/11575H01L27/11582H01L21/311H01L21/3213
CPCH01L21/31144H01L21/32139H10B69/00H10B41/50H10B41/27H10B43/50H10B43/27
Inventor 李飞孙文辞刘云飞陈琳胡军王猛
Owner YANGTZE MEMORY TECH CO LTD
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