Complementary
LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively
high voltage may be realized in a mixed-technology
integrated circuit of the so-called "
smart power" type, by forming a
phosphorus doped n-region of a similar
diffusion profile, respectively in: The drain zone of the n-channel
LDMOS transistors, in the body zone of the p-channel
LDMOS transistors forming first
CMOS structures; in the drain zone of n-channel MOS transistors belonging to second
CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the
voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing
CMOS stages capable of operating at a relatively
high voltage (of about 20V) thus permitting a direct
interfacing with VDMOS power devices without requiring any "
level shifting" stages. The whole
integrated circuit has less
interfacing problems and improved electrical and reliability characteristics.