A capacitance readout circuit for secondary summation of cross-sampling charge, which is a symmetrical circuit structure, including switches 1, 2, 5, 6 for charging the sensor capacitance, reference capacitor arrays CR1 and CR2, and for charging the reference Switches 3, 4, 7, 8 for charging the capacitor array, switches 9, 10, 11, 12, 13, 14, 15, 18 for charge transfer, capacitors CD1 and CD2 for offset cancellation and low frequency noise suppression, and The switches 16 and 17 that provide the DC operating point for the circuit, the fully differential transconductance operational amplifier, the integrating capacitors CI1 and CI2 for storing the transferred charges, the integrating capacitors CI3, CI4 and switches 22 and 23 for adjusting the circuit gain, and the For the switches 19, 20, 21, 24 that provide DC bias for the fully differential transconductance inputs, the entire readout circuit is controlled by a 4-phase non-overlapping clock circuit.