21198results about "Efficient regulation technologies" patented technology

An apparatus for controlling the speed of an AC motor comprising a switch adapted to be coupled in parallel with power terminals for the AC motor; a capacitor coupled in series with the parallel combination of the switch and the motor; the capacitor adapted to provide an AC supply voltage from an AC source to the parallel circuit comprising the motor and the switch; and a control circuit for controlling the conduction time of the switch in order to vary the speed of the motor. The switch is preferably pulse-width modulated at a frequency twice the line frequency of the AC supply voltage, and the switch is turned on when the voltage across the AC motor is zero volts. The apparatus is operable to provide for continuously variable control of the motor speed while minimizing acoustic noise in the motor.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A double-ended variable speed blower for Continuous Positive Airway Pressure (CPAP) ventilation of patients includes two impellers in the gas flow path that cooperatively pressurize gas to desired pressure and flow characteristics. Thus, the double-ended blower can provide faster pressure response and desired flow characteristics over a narrower range of motor speeds, resulting in greater reliability and less acoustic noise.

In an ejector cycle system using carbon dioxide as refrigerant, an ejector decompresses and expands refrigerant from a radiator to suck gas refrigerant evaporated in an evaporator, and converts an expansion energy to a pressure energy to increase a refrigerant pressure to be sucked into a compressor. Because refrigerant is decompressed and expanded in a super-critical area, a pressure difference during the decompression operation becomes larger, and a specific enthalpy difference becomes larger. Accordingly, energy converting efficiency in the ejector becomes higher, and efficiency of the ejector cycle system is improved.