An architecture for a reconfigurable network that can be implemented on a
semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable
network on a
chip is disclosed, which includes aspects of
reconfigurable computing,
system on a
chip, and
network on a chip designs. More precisely, a reconfigurable
network on a chip includes a
general purpose microprocessor for implementing
software tasks, a plurality of on-chip memories for facilitating the
processing of large data structures as well as processor
collaboration, a plurality of reconfigurable execution units including self-contained, individually reconfigurable programmable logic arrays, a plurality of configurable
system interface units that provide interconnections between on-chip memories, networks or buses, an on-chip network including a network
interconnection interface that enables communication between all reconfigurable execution units, configurable
system interface units and
general purpose microprocessors, a
fine grain interconnect unit that gathers associated input / output signals for a particular interface and attaches them to a designated
system interface resource, and a plurality of input / output blocks that supply the link between an on-chip interface resource and a particular external network or device interface. Advantageously, the network minimizes the configuration latency of the reconfigurable execution units and also enables reconfiguration on-the-fly.