36results about How to "Allow for any form" patented technology

A rotatable multi-operation tool for chip removing machining, including a plurality of replaceable cutting inserts of different types, and a basic body that is rotatable around a center axis and includes a rear end and a front end from which there is extending rearward an envelope surface in which at least one chip space, delimited by two opposite side surfaces, is countersunk, which opens in the envelope surface and in the front end. A first cutting insert is mounted in a first insert seat that is formed in one side surface of the chip space and situated in the immediate vicinity of the front end and included in a cavity that opens in the front end for the cutting insert to partly protrude axially forward from the front end. A second cutting insert, of a type other than the first cutting insert, is mounted in a second insert seat, which is formed in the same side surface as the first insert seat and situated axially behind the first insert seat. The second insert seat is included in a cavity that opens in a part of the envelope surface.

A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die mounted on a substrate. A conductive layer is deposited in the at least one cavity that substantially fills the space between the at least one cavity and the at least one die when the lid is coupled to the substrate.

A method of processing a semiconductor device is disclosed and comprises patterning a multi-layer photoresist which comprises an imaging layer overlying an underlying layer. The patterning of the resist defines an exposed portion of an underlying process layer. The method further comprises inspecting the patterned multi-layer photoresist for defects and re-working the patterned multi-layer photoresist upon a failed inspection. The re-work process comprises depositing a protection layer over the patterned multi-layer photoresist and over the exposed portion of the underlying process layer. A portion of the protection layer and the imaging layer are then removed in a concurrent manner while leaving a remaining portion of the protection layer covering the exposed portion of the underlying process layer. A remaining portion of the protection layer and the underlying layer are then removed in a concurrent manner and such removal does not adversely impact the process layer.

In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.